3–10 GHz low-power, low-noise CMOS distributed amplifier using splitting-load inductive peaking and noise-suppression techniques

2009 ◽  
Vol 45 (20) ◽  
pp. 1033 ◽  
Author(s):  
J.-F. Chang ◽  
Y.-S. Lin
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.


2011 ◽  
Vol E94-C (10) ◽  
pp. 1698-1701
Author(s):  
Yang SUN ◽  
Chang-Jin JEONG ◽  
In-Young LEE ◽  
Sang-Gug LEE

2021 ◽  
Vol 324 ◽  
pp. 112681
Author(s):  
Jianhui Sun ◽  
Zibin Wang ◽  
Tongxi Wang ◽  
Guozhu Liu ◽  
Jiangwei Tian
Keyword(s):  

2021 ◽  
Author(s):  
Rafael Vieira ◽  
Nuno Horta ◽  
Nuno Lourenço ◽  
Ricardo Póvoa

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