Design of high speed 2-stage OTA for high capacitive load of 120pF and 2.96V

High speed operational transconductance amplifier (OTA) is used to drive high capacitive loads to reduce the charging time while providing adequate gain and stability. A 2-stage amplifier is proposed to provide high slew rate and sufficient gain and stability. 45nm process technology is used to compare performance with differential and telescopic amplifier designs. Resistive feedback and noise-gain compensation techniques are used to drive 120pF load and provide 2.96V at output for a high slew rate of 2.2V/µs.

A design methodology for programmable-gain low-noise TIA in CMOS

The work reports on the design of an area-efficient inductor-less low-noise CMOS transimpedance amplifier suitable for entry-level optical time-domain reflectometers. The work suggests a novel approach for implementing a programmable-gain in capacitive feedback TIA with an independent adjustment of the low- and high-frequency behavior using the input stage biasing impedance and one of the feedback capacitors. The approach addresses a typical noise problem of fast feed-forward or resistive feedback topologies while alleviating the trade-off of the key TIA performance indicators. A more accurate amplifier model is proposed which takes into account the effects due to capacitive isolation and both biasing circuits. Further modifications to the reference design are suggested including the PMOS-based implementation of the biasing circuit to address the voltage headroom issue. The circuit was implemented using a standard 180 nm CMOS process and operates from 1.8 V supply with the drawn current of 11.7 mA.

Development of intelligent preamplifier for semiconductor detectors

The results of engineering an intelligent preamplifier for HPGe gamma-detectors are presented. An intelligent preamplifier is a low-noise, high-speed resistive feedback charge-sensitive preamplifier with a built-in microcontroller and additional units that enable control of preamplifier and detector parameters. It also allows to manage performance of the internal testing pulser, sensor of liquid nitrogen level in Dewar, humidity, pressure and temperature sensors in a sealed preamplifier section. Intelligent preamplifier operation, setup and parameter measurements are controlled by a software.

An Ultra-Wideband 0.1–6.1 GHz Low Noise Amplifier in 180 nm CMOS Technology

In this paper, an Ultra-Wideband (UWB) low noise amplifier (LNA) with low power consumption and high-power gain in 180[Formula: see text]nm CMOS technology is presented. An innovative combination of conventional methods to design UWB-LNA, i.e., resistive-feedback, inductive-series peaking, noise cancelling and inductive degeneration techniques is described here. The proposed LNA consists of two common source amplifiers with resistive feedback in which the noise and power consumption have been reduced by using the noise cancelling and current reuse techniques, respectively. Also, resistive feedback in the first stage reduces input resistance, hereby improving input impedance matching. In the second stage, which is used to increase the power gain, a common source structure with inductive-series peaking and noise cancellation techniques is used. The analytical results agree well with the post layout simulation results. The post-layout simulation shows a gain of [Formula: see text][Formula: see text]dB and noise figure (NF) of 2.3[Formula: see text]dB in the whole [Formula: see text][Formula: see text]dB bandwidth of 0.1[Formula: see text]GHz to 6.1[Formula: see text]GHz, while the S11 and S22 are less than [Formula: see text][Formula: see text]dB. The proposed circuit has a figure of merit of 9.9 which is significantly improved compared to the previous works. The total power dissipation is only 7.3[Formula: see text]mW, and the active area is less than 0.7[Formula: see text]mm2.

Symmetrically scaled coexisting behaviors in two types of simple jerk circuits

Purpose The purpose of this paper is to develop two types of simple jerk circuits and to carry out their dynamical analyses using a unified mathematical model. Design/methodology/approach Two types of simple jerk circuits only involve a nonlinear resistive feedback channel composited by a nonlinear device and an inverter. The nonlinear device is implemented through parallelly connecting two diode-switch-based series branches. According to the classifications of switch states and circuit types, a unified mathematical model is established for these two types of simple jerk circuits, and the origin symmetry and scale proportionality along with the origin equilibrium stability are thereby discussed. The coexisting bifurcation behaviors in the two types of simple jerk systems are revealed by bifurcation plots, and the origin symmetry and scale proportionality are effectively demonstrated by phase plots and attraction basins. Moreover, hardware experimental measurements are performed, from which the captured results well validate the numerical simulations. Findings Two types of simple jerk circuits are unified through parallelly connecting two diode-switch-based series branches and a unified mathematical model with six kinds of nonlinearities is established. Especially, the origin symmetry and scale proportionality for the two types of simple jerk systems are discussed quantitatively. These jerk circuits are all simple and inexpensive, easy to be physically implemented, which are helpful to explore chaos-based engineering applications. Originality/value Unlike previous works, the significant values are that through unifying these two types of simple jerk systems, a unified mathematical model with six kinds of nonlinearities is established, upon which symmetrically scaled coexisting behaviors are numerically disclosed and experimentally demonstrated.