scholarly journals New SRRC receiver filter design with reduced number of filter taps for wireless communication systems

2018 ◽  
Vol 12 (9) ◽  
pp. 1128-1133
Author(s):  
Hoon Kang ◽  
Jong-Seon No
IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 98786-98791 ◽  
Author(s):  
Jianchun Xu ◽  
Ke Bi ◽  
Xiaojun Zhai ◽  
Yanan Hao ◽  
Klaus D. Mcdonald-Maier

Author(s):  
Sunil Raosaheb Gagare . ◽  
Dolly Reney .

The new design methods of microwave filter has proved its significance for use in wireless communication systems. Modern wireless communication systems require microwave filters to have stringent specifications such as compact size, robust, conformal, light weight and more importantly cost effective while maintaining its electrical characteristics. Micro-strip filter design and reconfigurable filters present a better prospectus in this regards as it meets the specifications of modern wireless communication applications. Reconfigurable filters can provide control over parameters such as frequency, bandwidth and selectivity while reducing the need of number of switches sandwiched between electrical components. Different methods have provided a new dimension for designing microwave filters .In this article, we present a review on design methods for reconfigurable band-pass filters for next generation wireless technologies such as 4G, 5G and IOT.


Author(s):  
A. Suresh Babu ◽  
B. Anand

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.


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