Integrated higher‐order pulse‐width modulation filter–transformer structure for single‐phase static compensator

2013 ◽  
Vol 6 (1) ◽  
pp. 67-77 ◽  
Author(s):  
D. Venkatramanan ◽  
Vinod John
2021 ◽  
Vol 2107 (1) ◽  
pp. 012051
Author(s):  
M. Z. Aihsan ◽  
A. M. Yusof ◽  
Hasliza A Rahim ◽  
B. Ismail ◽  
W. A. Mustafa ◽  
...  

Abstract This article organized in two sections where it compares the performance of single-phase inverters using various types of inductors with differences modulation technique of pulse width modulation (PWM). Not all inductors perform the same function, even the inductance value is the same. The study will investigate the capability of each inductor on its performance to convert the unfiltered AC voltage into filtered sinusoidal AC voltage. The drum core and toroidal core inductors were used in this investigation. For both inductors, the performance will be analyzed based on Bipolar and Unipolar switching schemes in a single unit H-bridge circuit. The validation of results are through experimental assessment only and it will be evaluating the shape of sinusoidal AC voltage and the content of total harmonics distortion in the AC voltage for both inductors.


Energies ◽  
2020 ◽  
Vol 13 (2) ◽  
pp. 434 ◽  
Author(s):  
Xiumei Yue ◽  
Hongliang Wang ◽  
Xiaonan Zhu ◽  
Xinwei Wei ◽  
Yan-Fei Liu

Single-phase full-bridge transformerless topologies, such as the H5, H6, or the highly efficient and reliable inverter concept (HERIC) topologies, are commonly used for leakage current suppression for photovoltaic (PV) applications. The main derivation methodology of full-bridge topologies has been used based on both a DC-based decoupling model and an AC-based decoupling model. However, this methodology is not suited to the search for all possible topologies, and cannot verify whether they are inclusive. Part I of this paper will propose a new topology derivation methodology based on unipolar sinusoidal pulse width modulation (USPWM) to search all possible full-bridge topologies for leakage current suppression. First of all, a unified circuit model is proposed, instead of the DC- and AC-based models. Secondly, a mathematic method called the MN principle is then proposed to search for all possible topologies, and a derivation procedure is provided. It was verified that all existing topologies could be found using the proposed method; furthermore, seven new topologies were derived. The proposed topology derivation methodology is extended to search topologies under Double-Frequency USPWM (DFUSPWM). Twenty topologies under USPWM and four topologies under DFUSPWM have been derived.


2013 ◽  
Vol 3 (4) ◽  
Author(s):  
Subhash Chander ◽  
Pramod Agarwal ◽  
Indra Gupta

AbstractPulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA’s advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.


2013 ◽  
Vol 534 ◽  
pp. 227-232
Author(s):  
Yasushi Yuminaka ◽  
Shingo Ishida ◽  
Kenichi Henmi

In this paper, a Pulse-Width Modulation (PWM) pre-emphasis technique is extended to a2nd-order version to equalize a higher-order transfer function of an interconnection inside/betweenVLSI chips. The PWM pre-emphasis method does not change the pulse amplitude as for conventionalFIR pre-emphasis, but instead exploits timing resolution. As a proof of concept, a 2nd-order timedomainpre-emphasis technique is designed and implemented using an FPGA to demonstrate thecapability of compensating for deterioration of signals caused by interconnections with higher-ordertransfer functions.


Sign in / Sign up

Export Citation Format

Share Document