The application of a Hamming error correcting code to a standard teletype equipment

1961 ◽  
Vol 22 (5) ◽  
pp. 377-392
Author(s):  
R.W. Levell
Keyword(s):  
Error Correcting Code ◽  
Hamming Error Correcting Code

New Approach to Salve Single Event Upsets Faults in Satellite Communications

2011 ◽  
Vol 110-116 ◽  
pp. 4161-4165
Author(s):  
Mahoomd Ghodratian ◽  
Ashkan Masoomi ◽  
Roozbeh Hamzehyan ◽  
Najmeh Cheraghi Shirazi
Keyword(s):  
Detailed Analysis ◽  
Error Correcting Code ◽  
Satellite Communications ◽  
Radiation Environment ◽  
Single Event ◽  
Imaging Data ◽  
Single Event Upsets ◽  
Ground Station ◽  
Hamming Error Correcting Code ◽  
The Impact

The encrypted satellite data can get corrupted before reaching the ground station due to various faults. One major source of faults is the harsh radiation environment. Single Even Upset (SEU) faults can occur on-board during encryption due to radiation. This paper presents a novel model to detect and correct Single Event Upsets in on-board implementations of the AES algorithm, which is based on Hamming error correcting code. From five modes of AES, CRT mode seems to be the best mode to encrypt satellite video and image links. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out. In this paper the impact of these faults on the data is discussed and compared for all the five modes of AES. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out.

scholarly journals In-Memory Hamming Error-Correcting Code in Memristor Crossbar

2021 ◽  
Author(s):  
Woorham Bae ◽  
Jin-Woo Han ◽  
Kyung Jean Yoon
Keyword(s):  
Integrated Circuit ◽  
Error Correcting Code ◽  
Current Mode ◽  
Cmos Process ◽  
Logic Device ◽  
Resistance State ◽  
Hamming Error Correcting Code ◽  
Memristor Crossbar ◽  
Exclusive Or ◽  
And Storage

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

scholarly journals In-Memory Hamming Error-Correcting Code in Memristor Crossbar

2021 ◽  
Author(s):  
Woorham Bae ◽  
Jin-Woo Han ◽  
Kyung Jean Yoon
Keyword(s):  
Integrated Circuit ◽  
Error Correcting Code ◽  
Current Mode ◽  
Cmos Process ◽  
Logic Device ◽  
Resistance State ◽  
Hamming Error Correcting Code ◽  
Memristor Crossbar ◽  
Exclusive Or ◽  
And Storage

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

An error-correcting code framework for genetic sequence analysis

2004 ◽  
Vol 341 (1-2) ◽  
pp. 89-109 ◽  
Author(s):  
Elebeoba E. May ◽  
Mladen A. Vouk ◽  
Donald L. Bitzer ◽  
David I. Rosnick
Keyword(s):  
Sequence Analysis ◽  
Error Correcting Code ◽  
Genetic Sequence ◽  
Genetic Sequence Analysis

scholarly journals An Application of p-Fibonacci Error-Correcting Codes to Cryptography

Mathematics ◽  
2021 ◽  
Vol 9 (7) ◽  
pp. 789
Author(s):  
Emanuele Bellini ◽  
Chiara Marcolla ◽  
Nadir Murru
Keyword(s):  
Error Correcting Code ◽  
Error Correcting Codes ◽  
Multiparty Computation ◽  
Zero Knowledge ◽  
Signature Schemes ◽  
Standardization Process ◽  
Technology Standardization

In addition to their usefulness in proving one’s identity electronically, identification protocols based on zero-knowledge proofs allow designing secure cryptographic signature schemes by means of the Fiat–Shamir transform or other similar constructs. This approach has been followed by many cryptographers during the NIST (National Institute of Standards and Technology) standardization process for quantum-resistant signature schemes. NIST candidates include solutions in different settings, such as lattices and multivariate and multiparty computation. While error-correcting codes may also be used, they do not provide very practical parameters, with a few exceptions. In this manuscript, we explored the possibility of using the error-correcting codes proposed by Stakhov in 2006 to design an identification protocol based on zero-knowledge proofs. We showed that this type of code offers a valid alternative in the error-correcting code setting to build such protocols and, consequently, quantum-resistant signature schemes.

scholarly journals Palmprint Based Multidimensional Fuzzy Vault Scheme

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Hailun Liu ◽  
Dongmei Sun ◽  
Ke Xiong ◽  
Zhengding Qiu
Keyword(s):  
Error Correcting Code ◽  
Experimental Results ◽  
Fuzzy Vault ◽  
Biometric Template ◽  
Template Protection ◽  
Biometric Template Protection

Fuzzy vault scheme (FVS) is one of the most popular biometric cryptosystems for biometric template protection. However, error correcting code (ECC) proposed in FVS is not appropriate to deal with real-valued biometric intraclass variances. In this paper, we propose a multidimensional fuzzy vault scheme (MDFVS) in which a general subspace error-tolerant mechanism is designed and embedded into FVS to handle intraclass variances. Palmprint is one of the most important biometrics; to protect palmprint templates; a palmprint based MDFVS implementation is also presented. Experimental results show that the proposed scheme not only can deal with intraclass variances effectively but also could maintain the accuracy and meanwhile enhance security.

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