scholarly journals In-Memory Hamming Error-Correcting Code in Memristor Crossbar

Author(s):  
Woorham Bae ◽  
Jin-Woo Han ◽  
Kyung Jean Yoon

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

2021 ◽  
Author(s):  
Woorham Bae ◽  
Jin-Woo Han ◽  
Kyung Jean Yoon

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.


Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1603
Author(s):  
Minji Cho ◽  
Heechul Lee ◽  
Doohyung Woo

In this study, a novel IR projector driver that can minimize nonuniformity in electric circuits, using a dual-current-programming structure, is proposed to generate high-quality infrared (IR) scenes for accurate sensor evaluation. Unlike the conventional current-mode structure, the proposed system reduces pixel-to-pixel nonuniformity by assigning two roles (data sampling and current driving) to a single transistor. A prototype of the proposed circuit was designed and fabricated using the SK-Hynix 0.18 µm CMOS process, and its performance was analyzed using post-layout simulation data. It was verified that nonuniformity, which is defined as the standard deviation divided by the mean radiance, could be reduced from 21% to less than 0.1%.


2019 ◽  
Vol 29 (10) ◽  
pp. 2050162 ◽  
Author(s):  
Data R. Bhaskar ◽  
Ajishek Raj ◽  
Pragati Kumar

This paper introduces an electronically tunable mixed-mode universal biquad filter configuration employing four single output operational transconductance amplifiers (OTAs), one dual output OTA and two grounded capacitors (GCs) (ideal for integrated circuit implementation and absorbing shunt parasitic capacitances). The presented structure can realize all second-order filter functions, namely, low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) using appropriate selection(s) of input signals. The cut-off frequency ([Formula: see text] and bandwidth (BW) of the realized filters can be tuned orthogonally through the transconductance (by varying the bias currents) of the OTAs. The proposed biquad configuration enjoys low active and passive sensitivities. The workability of this multifunctional biquad filter topology has been confirmed through simulations using MATLAB and Analog Design Environment (ADE) spectre tool provided by Cadence Virtuoso, using 0.18[Formula: see text][Formula: see text]m CMOS process parameter. The post-layout simulations have also been carried out to validate the theory.


Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.


2013 ◽  
Vol 22 (09) ◽  
pp. 1340001 ◽  
Author(s):  
JIUN-WEI HORNG ◽  
TO-YAO CHIU ◽  
CHING-PAO HSIAO ◽  
GUANG-TING HUANG

A current-mode universal biquadratic filter with three input terminals and one output terminal is presented. The architecture uses two current conveyors (CCs), two grounded capacitors and two grounded resistors; and can realize all standard second-order filter functions — highpass, bandpass, lowpass, notch and allpass. Moreover, the circuit still offers the following advantage features: very low active and passive sensitivities, using of grounded capacitors and resistors which is ideal for integrated circuit implementation, without requirements for critical component matching conditions and very high output impedance. The workability of the proposed circuit has been verified via HSPICE simulations using TSMC 0.18 μm, level 49 MOSFET technology.


Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.


2021 ◽  
Vol 25 (2) ◽  
pp. 65-76
Author(s):  
Tajinder Singh Arora ◽  

This research article explores the possible applications of voltage differencing current conveyor (VDCC), as a current mode universal filter and a sinusoidal oscillator. Without the need for an additional active/passive element, a very simple hardware modification makes it a dual-mode quadrature oscillator from the filter configuration. Both the proposed circuit requires only two VDCC and all grounded passive elements, hence a preferable choice for integration. The filter has some desirable features such as availability of all five explicit outputs, independent tunability of filter parameters. Availability of explicit quadrature current outputs, independence in start and frequency of oscillations, makes it a better oscillator design. Apart from prevalent CMOS simulation results, VDCC is also realized and experimentally tested using the off-the-shelf integrated circuit. All the pen and paper analysis such as non-ideal, sensitivity and parasitic analysis supports the design.


2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.


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