An Image Authentication and Tampered Detection Scheme Exploiting Local Binary Pattern Along with Hamming Error Correcting Code

2021 ◽  
Author(s):  
Pabitra Pal ◽  
Biswapati Jana ◽  
Jaydeb Bhaumik
Keyword(s):  
Local Binary Pattern ◽  
Error Correcting Code ◽  
Image Authentication ◽  
Detection Scheme ◽  
Hamming Error Correcting Code

Combining Digital Signature with Local Binary Pattern-Least Significant Bit Steganography Techniques for Securing Medical Images

2020 ◽  
Vol 10 (6) ◽  
pp. 1288-1293
Author(s):  
K. N. Madhusudhan ◽  
P. Sakthivel
Keyword(s):  
Digital Signature ◽  
Local Binary Pattern ◽  
Medical Images ◽  
Image Authentication ◽  
Reversible Watermarking ◽  
Cover Image ◽  
Least Significant Bit ◽  
New Approach ◽  
Different Types ◽  
Separate File

The image authentication is generally based on two different types of techniques: watermarking and digital signature. In watermarking methods, embedded watermarking is often imperceptible and it contains either a specific ID of producer or codes related to content that are used for authentication. Normally a separate file is stored, digital signature is a non-repudiation and encrypted version of the information extracted from the data. A digital signature can be attached to the data to prove the originality and integrity. The proposed work presents a new approach to steganography of medical images that uses modified Least Significant Bit (LSB) based on the Local Binary Pattern (LBP) pattern. As a first step, cover image has been divided as blocks of 3×3 non overlapping masks. Then, the pixel embedding position (clock wise or anti-clock wise) has to be identified using LBP operator. The value of the LBP operator determines how and where to embed secret image pixel. Later, using LSB method, pixel values will be embedded in the cover image pixel. In order to provide the integrity of the data, the proposed work also presents Reversible Watermarking (RW), a Digital Signature (DS) technique. The proposed algorithm of steganography experimented on few medical images and achieved better efficiency with respect to MSE and PSNR values and same is reported in this paper.

New Approach to Salve Single Event Upsets Faults in Satellite Communications

2011 ◽  
Vol 110-116 ◽  
pp. 4161-4165
Author(s):  
Mahoomd Ghodratian ◽  
Ashkan Masoomi ◽  
Roozbeh Hamzehyan ◽  
Najmeh Cheraghi Shirazi
Keyword(s):  
Detailed Analysis ◽  
Error Correcting Code ◽  
Satellite Communications ◽  
Radiation Environment ◽  
Single Event ◽  
Imaging Data ◽  
Single Event Upsets ◽  
Ground Station ◽  
Hamming Error Correcting Code ◽  
The Impact

The encrypted satellite data can get corrupted before reaching the ground station due to various faults. One major source of faults is the harsh radiation environment. Single Even Upset (SEU) faults can occur on-board during encryption due to radiation. This paper presents a novel model to detect and correct Single Event Upsets in on-board implementations of the AES algorithm, which is based on Hamming error correcting code. From five modes of AES, CRT mode seems to be the best mode to encrypt satellite video and image links. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out. In this paper the impact of these faults on the data is discussed and compared for all the five modes of AES. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out.

scholarly journals Color Image Self-Recovery and Tampering Detection Scheme Based on Fragile Watermarking with High Recovery Capability

2021 ◽  
Vol 11 (7) ◽  
pp. 3187
Author(s):  
Rogelio Reyes-Reyes ◽  
Clara Cruz-Ramos ◽  
Volodymyr Ponomaryov ◽  
Beatriz P. Garcia-Salgado ◽  
Javier Molina-Garcia
Keyword(s):  
Image Quality ◽  
Color Image ◽  
Image Authentication ◽  
Extraction Process ◽  
Fragile Watermarking ◽  
Superior Performance ◽  
Coincidence Problem ◽  
Detection Scheme ◽  
Tampered Image ◽  
Exclusive Or

In this paper, a fragile watermarking scheme for color image authentication and self-recovery with high tampering rates is proposed. The original image is sub-sampled and divided into non-overlapping blocks, where a watermark used for recovery purposes is generated for each one of them. Additionally, for each recovery watermark, the bitwise exclusive OR (XOR) operation is applied to obtain a single bit for the block authentication procedure. The embedding and extraction process can be implemented in three variants (1-LSB, 2-LSB or 3-LSB) to solve the tampering coincidence problem (TCP). Three, six or nine copies of the generated watermarks can be embedded according to the variant process. Additionally, the embedding stage is implemented in a bit adjustment phase, increasing the watermarked image quality. A particular procedure is applied during a post-processing step to detect the regions affected by the TCP in each recovery watermark, where a single faithful image used for recovery is generated. In addition, we involve an inpainting algorithm to fill the blocks that have been tampered with, significantly increasing the recovery image quality. Simulation results show that the proposed framework demonstrates higher quality for the watermarked images and an efficient ability to reconstruct tampered image regions with extremely high rates (up to 90%). The novel self-recovery scheme has confirmed superior performance in reconstructing altered image regions in terms of objective criteria values and subjective visual perception via the human visual system against other state-of-the-art approaches.

scholarly journals In-Memory Hamming Error-Correcting Code in Memristor Crossbar

2021 ◽  
Author(s):  
Woorham Bae ◽  
Jin-Woo Han ◽  
Kyung Jean Yoon
Keyword(s):  
Integrated Circuit ◽  
Error Correcting Code ◽  
Current Mode ◽  
Cmos Process ◽  
Logic Device ◽  
Resistance State ◽  
Hamming Error Correcting Code ◽  
Memristor Crossbar ◽  
Exclusive Or ◽  
And Storage

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

scholarly journals In-Memory Hamming Error-Correcting Code in Memristor Crossbar

2021 ◽  
Author(s):  
Woorham Bae ◽  
Jin-Woo Han ◽  
Kyung Jean Yoon
Keyword(s):  
Integrated Circuit ◽  
Error Correcting Code ◽  
Current Mode ◽  
Cmos Process ◽  
Logic Device ◽  
Resistance State ◽  
Hamming Error Correcting Code ◽  
Memristor Crossbar ◽  
Exclusive Or ◽  
And Storage

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

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