In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

New Approach to Salve Single Event Upsets Faults in Satellite Communications

The encrypted satellite data can get corrupted before reaching the ground station due to various faults. One major source of faults is the harsh radiation environment. Single Even Upset (SEU) faults can occur on-board during encryption due to radiation. This paper presents a novel model to detect and correct Single Event Upsets in on-board implementations of the AES algorithm, which is based on Hamming error correcting code. From five modes of AES, CRT mode seems to be the best mode to encrypt satellite video and image links. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out. In this paper the impact of these faults on the data is discussed and compared for all the five modes of AES. A detailed analysis of the effect of SEUs on the imaging data during on-board encryption using the modes of AES is carried out.