Evolution and modulation of Ag filament dynamics within memristive devices based on necklace-like Ag@TiO2 nanowire networks

Random nanowire networks (NWNs) are regarded as promising memristive materials for applications in information storage, selectors, and neuromorphic computing. The further insight to understand their resistive switching properties and conduction mechanisms is crucial to realize the full potential of random NWNs. Here, a novel planar memristive device based on necklace-like structure Ag@TiO2 NWN is reported, in which a strategy only using water to tailor the TiO2 shell on Ag core for necklace-like core-shell structure is developed to achieve uniform topology connectivity. With analyzing the influence of compliance current on resistive switching characteristics and further tracing evolution trends of resistance state during the repetitive switching cycles, two distinctive evolution trends of low resistance state failure and high resistance state failure are revealed, which bear resemblance to memory loss and consolidation in biological systems. The underlying conduction mechanisms are related to the modulation of the Ag accumulation dynamics inside the filaments at cross-point junctions within conductive paths of NWNs. An optimizing principle is then proposed to design reproducible and reliable threshold switching devices by tuning the NWN density and electrical stimulation. The optimized threshold switching devices have a high ON/OFF ratio of ~107 with threshold voltage as low as 0.35 V. This work will provide insights into engineering random NWNs for diverse functions by modulating external excitation and optimizing NWN parameters to satisfy specific applications, transforming from neuromorphic systems to threshold switching devices as selectors.

Building resistive switching memory having super-steep switching slope with in-plane boron nitride

The two-dimensional hexagonal boron nitride (h-BN) has been used as resistive switching (RS) material for memory due to its insulation, good thermal conductivity and excellent thermal/chemical stability. A typical h-BN based RS memory employs a Metal-Insulator-Metal (MIM) vertical structure, in which metal ions pass through the h-BN layers to realize the transition from high resistance state (HRS) to low resistance state (LRS). Alternatively, just like the horizontal structure widely used in the traditional MOS capacitor based memory, the performance of in-plane h-BN memory should also be evaluated to determine its potential applications. As consequence, a horizontal structured resistive memory has been designed in this work by forming freestanding h-BN across Ag nanogap, where the two-dimensional h-BN favored in-plane transport of metal ions to emphasize the RS behavior. As a result, the memory devices showed switching slope down to 0.25 mV/dec, ON/OFF ratio up to 1E8, SET current down to pA and SET voltage down to 180 mV.

Flexible Memory Device Composed of Metal-Oxide and Two-Dimensional Material (SnO2/WTe2) Exhibiting Stable Resistive Switching

Two-terminal, non-volatile memory devices are the fundamental building blocks of memory-storage devices to store the required information, but their lack of flexibility limits their potential for biological applications. After the discovery of two-dimensional (2D) materials, flexible memory devices are easy to build, because of their flexible nature. Here, we report on our flexible resistive-switching devices, composed of a bilayer tin-oxide/tungsten-ditelluride (SnO2/WTe2) heterostructure sandwiched between Ag (top) and Au (bottom) metal electrodes over a flexible PET substrate. The Ag/SnO2/WTe2/Au flexible devices exhibited highly stable resistive switching along with an excellent retention time. Triggering the device from a high-resistance state (HRS) to a low-resistance state (LRS) is attributed to Ag filament formation because of its diffusion. The conductive filament begins its development from the anode to the cathode, contrary to the formal electrochemical metallization theory. The bilayer structure of SnO2/WTe2 improved the endurance of the devices and reduced the switching voltage by up to 0.2 V compared to the single SnO2 stacked devices. These flexible and low-power-consumption features may lead to the construction of a wearable memory device for data-storage purposes.

Enhanced switching ratio of sol–gel-processed Y2O3 RRAM device by suppressing oxygen-vacancy formation at high annealing temperature

Sol–gel-processed Y2O3 films were used as an active-channel layer for RRAM devices. The effect of post-annealing temperature on structural, chemical, and electrical characteristics was investigated. The Y2O3-RRAM devices, comprising electrochemically active metal electrodes, Ag, and Indium tin oxide (ITO) electrodes exhibited the conventional bipolar RRAM device operation. The fabricated Ag/Y2O3/ITO RRAM devices, comprising 500-℃ annealed Y2O3 films, exhibited less oxygen vacancy and defect, which reduced the leakage current and boosted high-resistance state/low-resistance state ratio, more than 10^5, and promising nonvolatile memory properties without deterioration for 100 cycles and 10^4 seconds.

An Efficient and Flexible Window Function for Memristor Model and its Analog Circuit Application

The memristor is a nanostructure resistive tuning two terminal novel electronics device that has been widely explored in the area of neuromorphic computing systems, memories, digital circuits, analog circuits and many more new applications. In this article an efficient and flexible window function is presented for linear drift memristor model. Propose window function provides a unique feature (controllable window function discontinuity) to linear drift memristor model by which DPHL (Distorted Pinched Hysteresis Loop) problem is resolved and also improved the programming resistance state of the memristor. Five control parameters are introduced in the presented window function, in order to fix the pre-existing problem (like boundary effect, boundary lock and inflexibility) and make it more flexible. The programmable analog gain amplifier circuit is ultimately executed to instantiate the utilization of evolved memristor model.

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

Phase fluctuations in conventional superconductors

Within the Bardeen-Cooper-Schrieffer (BCS) theory, superconductivity is entirely governed by the pairing energy scale, which gives rise to the superconducting energy gap, Δ. However, another important energy scale, the superfluid phase stiffness, J, which determines the resilience of the superconductor to phase-fluctuations is normally ignored. The spectacular success of BCS theory owes to the fact that in conventional superconductors J is normally several orders of magnitude larger than Δ and thus an irrelevant energy scale. However, in certain situations such as in the presence of low carrier density, strong disorder, at low-dimensions or in granular superconductors, J can drastically come down and even become smaller than Δ. In such situations, the temperature and magnetic field evolution of superconducting properties is governed by phase fluctuations, which gives rise to novel electronic states where signatures of electronic pairing continue to exist even when the zero resistance state is destroyed. In this article, we will review the recent experimental developments on the study of phase fluctuations in conventional superconductors.