High temperature surface imaging using atomic force microscopy

Abstract We demonstrate direct epitaxial growth of high-quality hexagonal boron nitride (hBN) layers on graphite using high-temperature plasma-assisted molecular beam epitaxy. Atomic force microscopy reveals mono- and few-layer island growth, while conducting atomic force microscopy shows that the grown hBN has a resistance which increases exponentially with the number of layers, and has electrical properties comparable to exfoliated hBN. X-ray photoelectron spectroscopy, Raman microscopy and spectroscopic ellipsometry measurements on hBN confirm the formation of sp2-bonded hBN and a band gap of 5.9 ± 0.1 eV with no chemical intermixing with graphite. We also observe hexagonal moiré patterns with a period of 15 nm, consistent with the alignment of the hBN lattice and the graphite substrate.

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Non Destructive Determination of the Threading Dislocation Density of Smooth Simox Substrates using Atomic Force Microscopy

Microscopy and Microanalysis ◽

10.1017/s1431927600037934 ◽

2000 ◽

Vol 6 (S2) ◽

pp. 1088-1089

Author(s):

A. Domenicucci ◽

R. Murphy ◽

D. Sadanna ◽

S. Klepeis

Keyword(s):

Atomic Force Microscopy ◽

High Temperature ◽

Single Crystal Silicon ◽

Silicon Layer ◽

High Dose ◽

Threading Dislocation ◽

Crystal Silicon ◽

Force Microscopy ◽

Atomic Force ◽

High Temperature Anneal

Atomic force microscopy (AFM) has been used extensively in recent years to study the topographic nature of surfaces in the nanometer range. Its high resolution and ability to be automated have made it an indispensable tool in semiconductor fabrication. Traditionally, AFM has been used to monitor the surface roughness of substrates fabricated by separation by implanted oxygen (SIMOX) processes. It was during such monitoring that a novel use of AFM was uncovered.A SIMOX process requires two basic steps - a high dose oxygen ion implantation (1017 to 1018 cm-3) followed by a high temperature anneal (>1200°C). The result of these processes is to form a buried oxide layer which isolates a top single crystal silicon layer from the underlying substrate. Pairs of threading dislocations can form in the top silicon layer during the high temperature anneal as a result of damage caused during the high dose oxygen implant.

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Real-Time Evolution of the Lamellar Organization of Poly(ethylene terephthalate) during Crystallization from the Melt: High-Temperature Atomic Force Microscopy Study

Macromolecules ◽

10.1021/ma010809b ◽

2001 ◽

Vol 34 (26) ◽

pp. 8944-8952 ◽

Cited By ~ 76

Author(s):

D. A. Ivanov ◽

Z. Amalou ◽

S. N. Magonov

Keyword(s):

Atomic Force Microscopy ◽

High Temperature ◽

Ethylene Terephthalate ◽

Microscopy Study ◽

Atomic Force Microscopy Study ◽

Force Microscopy ◽

Atomic Force ◽

Poly Ethylene Terephthalate ◽

Poly Ethylene ◽

Crystallization From The Melt

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Mitigation of BPD by Pre-Epigrowth High Temperature Substrate Annealing

Materials Science Forum ◽

10.4028/www.scientific.net/msf.858.233 ◽

2016 ◽

Vol 858 ◽

pp. 233-236 ◽

Cited By ~ 5

Author(s):

Nadeemullah A. Mahadik ◽

Robert E. Stahlbush ◽

Eugene A. Imhoff ◽

M.J. Tadjer ◽

G.E. Ruland ◽

...

Keyword(s):

Surface Roughness ◽

Atomic Force Microscopy ◽

High Temperature ◽

Surface Morphology ◽

Substrate Surface ◽

High Temperature Annealing ◽

Force Microscopy ◽

Atomic Force ◽

Substrate Annealing ◽

Edge Dislocations

Basal Plane Dislocations (BPD) intersecting the SiC substrate surface were converted to threading edge dislocations (TED) by high temperature annealing of the substrates in the temperature range of 1750 °C – 1950 °C. Successively, epitaxial growth on annealed as well as non-annealed samples was performed, concurrently, to investigate the effect of the substrate annealing on BPD mitigation in the epilayers. For the 1950 °C/10min anneal, a 3x reduction in BPD density was observed. Additionally, surface roughness measured using atomic force microscopy revealed no degradation in surface morphology of the grown epilayers after annealing.

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4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

Materials Science Forum ◽

10.4028/www.scientific.net/msf.527-529.1265 ◽

2006 ◽

Vol 527-529 ◽

pp. 1265-1268 ◽

Cited By ~ 1

Author(s):

Jeffery B. Fedison ◽

Chris S. Cowen ◽

Jerome L. Garrett ◽

E.T. Downey ◽

James W. Kretchmer ◽

...

Keyword(s):

Atomic Force Microscopy ◽

High Temperature ◽

Room Temperature ◽

Gate Oxide ◽

Surface Roughening ◽

Force Microscopy ◽

Atomic Force ◽

N Source ◽

High Temperature Anneal ◽

Blocking Voltage

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

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