Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

2012 ◽  
Vol 111 (7) ◽  
pp. 07E330 ◽  
Author(s):  
Kumiko Nomura ◽  
Keiko Abe ◽  
Hiroaki Yoda ◽  
Shinobu Fujita
Author(s):  
K. Hema ◽  
Muralidharan Muralidharan

<span lang="EN-IN">In this paper, we proposed to design a next-generation auto theft prevention system by adding significant enhancements and modernizing the existing security features</span><span lang="EN-IN">. </span><span lang="EN-IN">As vehicles turn out to be more refined, vehicle security frameworks must be more grounded than at any other time. A current vehicle uses remote keyless passage framework and Immobilizer framework as the primary weaponry against vehicle robbery. These structures avoid unapproved access of the vehicle to a particular degree, however, are not a secure one. Because of the straightforward and imperfect nature of these security frameworks, auto burglary occurrences worldwide are on the ascent. This venture needs a low power microcontroller however with elite prerequisites. LPC11C14 from NXP Semiconductors addresses these issues and in this manner picked as the primary MCU. It is an ultra-low-power ARM Cortex-M0 based microcontroller that can run up to 50MHz. It has 32KB of Flash memory and 8KB RAM. </span>


Author(s):  
Davide Rossi ◽  
Francesco Conti ◽  
Andrea Marongiu ◽  
Antonio Pullini ◽  
Igor Loi ◽  
...  

2013 ◽  
Vol 44 (7) ◽  
pp. 570-575 ◽  
Author(s):  
A. Mangla ◽  
M.-A. Chalkiadaki ◽  
F. Fadhuile ◽  
T. Taris ◽  
Y. Deval ◽  
...  

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  

2010 ◽  
Vol E93-C (6) ◽  
pp. 785-795
Author(s):  
Sung-Jin KIM ◽  
Minchang CHO ◽  
SeongHwan CHO
Keyword(s):  
Rfid Tag ◽  

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