Addressing crosstalk in crossbar memory arrays with a resistive switching ZnO homojunction diode

2021 ◽  
Vol 129 (20) ◽  
pp. 205106
Author(s):  
Punya Mainali ◽  
Lyndon D. Bastatas ◽  
Elena Echeverria ◽  
Phadindra Wagle ◽  
Prasanna Sankaran ◽  
...  
2016 ◽  
Vol 8 (35) ◽  
pp. 23348-23355 ◽  
Author(s):  
Ahmed Al-Haddad ◽  
Chengliang Wang ◽  
Haoyuan Qi ◽  
Fabian Grote ◽  
Liaoyong Wen ◽  
...  

2016 ◽  
Vol 46 (10) ◽  
pp. 107312
Author(s):  
ZhiWei ZONG ◽  
ZhuoYu JI ◽  
Ling LI ◽  
DeLong QIU ◽  
NianDuan LU ◽  
...  

2016 ◽  
Vol 120 (8) ◽  
pp. 084502 ◽  
Author(s):  
W. J. Duan ◽  
J. B. Wang ◽  
X. L. Zhong ◽  
H. J. Song ◽  
B. Li

Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.


2012 ◽  
Vol 27 (3) ◽  
pp. 323-326
Author(s):  
Zhen-Guo JI ◽  
Jun-Jie WANG ◽  
Qi-Nan MAO ◽  
Jun-Hua XI

2019 ◽  
Vol 9 (4) ◽  
pp. 486-493 ◽  
Author(s):  
S. Sahoo ◽  
P. Manoravi ◽  
S.R.S. Prabaharan

Introduction: Intrinsic resistive switching properties of Pt/TiO2-x/TiO2/Pt crossbar memory array has been examined using the crossbar (4×4) arrays fabricated by using DC/RF sputtering under specific conditions at room temperature. Materials and Methods: The growth of filament is envisaged from bottom electrode (BE) towards the top electrode (TE) by forming conducting nano-filaments across TiO2/TiO2-x bilayer stack. Non-linear pinched hysteresis curve (a signature of memristor) is evident from I-V plot measured using Pt/TiO2-x /TiO2/Pt bilayer device (a single cell amongst the 4×4 array is used). It is found that the observed I-V profile shows two distinguishable regions of switching symmetrically in both SET and RESET cycle. Distinguishable potential profiles are evident from I-V curve; in which region-1 relates to the electroformation prior to switching and region-2 shows the switching to ON state (LRS). It is observed that upon reversing the polarity, bipolar switching (set and reset) is evident from the facile symmetric pinched hysteresis profile. Obtaining such a facile switching is attributed to the desired composition of Titania layers i.e. the rutile TiO2 (stoichiometric) as the first layer obtained via controlled post annealing (650oC/1h) process onto which TiO2-x (anatase) is formed (350oC/1h). Results: These controlled processes adapted during the fabrication step help manipulate the desired potential barrier between metal (Pt) and TiO2 interface. Interestingly, this controlled process variation is found to be crucial for measuring the switching characteristics expected in Titania based memristor. In order to ensure the formation of rutile and anatase phases, XPS, XRD and HRSEM analyses have been carried out. Conclusion: Finally, the reliability of bilayer memristive structure is investigated by monitoring the retention (104 s) and endurance tests which ensured the reproducibility over 10,000 cycles.


2019 ◽  
Vol 1410 ◽  
pp. 012233 ◽  
Author(s):  
R V Tominov ◽  
N A Polupanov ◽  
V I Avilov ◽  
M S Solodovnik ◽  
N V Parshina ◽  
...  

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