scholarly journals A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 529-535
Author(s):  
A. T. Erdogan ◽  
T. Arslan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Digital Filters ◽  
Processing Algorithm ◽  
Block Processing ◽  
Segmentation Algorithms ◽  
Fir Digital Filters ◽  
Power Evaluation ◽  
Multiplier Circuit

A combined coefficient segmentation and block processing algorithm for low power implementation of FIR digital filters is described in this paper. The algorithm processes data and coefficients in blocks of fixed sizes. During the manipulation of each block, coefficients are segmented into two primitive components. The accumulative effect of processing a sequence of blocks and segmentation results in up to 80% reduction in power consumption in the multiplier circuit compared to conventional filtering. The paper describes the implementation of the algorithm, its constituent components, and the power evaluation environment developed. Simulations are performed using eight practical digital filter examples with various filter orders and data/coefficient wordlengths. In addition, the algorithm is compared with conventional filtering implementations and those using block processing and coefficient segmentation algorithms alone.

scholarly journals Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 397-403 ◽  
Author(s):  
S. Masupe ◽  
T. Arslan
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Vlsi Implementation ◽  
Dsp Processors ◽  
Power Evaluation ◽  
Multiplier Circuit

A generic multiplication scheme for the low power VLSI implementation of the DCT is described in this paper. The scheme concurrently processes blocks of cosine coefficient and pixel values during the multiplication procedure, with the aim of reducing the total switched capacitance within the multiplier circuit. The cosine coefficients, within each block, are manipulated such that some are processed using shift operations only. The remaining coefficients are presented to the multiplier inputs as a sequence, ordered according to bit correlation between successive cosine coefficients. The paper describes the multiplication scheme, the power evaluation environment used, and presents results, with a number of standard benchmark examples, demonstrating upto 50% power saving.

scholarly journals LOW POWER DIGITAL FILTERING USING ADAPTIVE APPROXIMATE PROCESSING: FIR FILTER STRUCTURES

2021 ◽  
pp. 1-5
Author(s):  
JEFFREY LUDWIG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Signal To Noise Ratio ◽  
Reducing Power ◽  
Digital Filtering ◽  
Low Power Design ◽  
Time Varying ◽  
Filtering Algorithms ◽  
Filter Structures

Techniques for reducing power consumption in digital circuits have become increasingly important because of the growing demand for portable multimedia devices. Digital filters, being ubiquitous in such devices, are a prime candidate for low power design. Algorithmic approaches to low power frequency-selective digital filtering which are based on the concepts of adaptive approximate processing have been developed and formalized by introducing the class of approximate filtering algorithms in which the order of a digital filter is dynamically varied to provide time-varying stopband attenuation in proportion to the time-varying signal-to-noise ratio (SNR) of the input signal, while maintaining a fixed SNR at the filter output. Since power consumption in digital filter implementations is proportional to the order of the filter, dynamically varying the filter order is a strategy which may be used to conserve power. In this paper we introduce a class of approximate filter structures using FIR digital filter constituent elements. These filter structures are explored and shown to be an important element in the characterization of approximate filtering algorithms.

scholarly journals Low Power Adder Based Digital Filter for QRS Detector

2014 ◽  
Vol 2014 ◽  
pp. 1-5
Author(s):  
L. Murali ◽  
D. Chitra ◽  
T. Manigandan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Full Adder ◽  
Leakage Power ◽  
System Level ◽  
Complex Signal ◽  
Verilog Hdl ◽  
Processing Elements ◽  
Signal Processors

Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

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