scholarly journals Low Power Adder Based Digital Filter for QRS Detector

2014 ◽  
Vol 2014 ◽  
pp. 1-5
Author(s):  
L. Murali ◽  
D. Chitra ◽  
T. Manigandan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Full Adder ◽  
Leakage Power ◽  
System Level ◽  
Complex Signal ◽  
Verilog Hdl ◽  
Processing Elements ◽  
Signal Processors

Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

scholarly journals Low Power Checks in Multi Voltage Designs

2020 ◽  
Vol 11 ◽  
pp. 105-111
Author(s):  
K. R. Haripriya ◽  
Ajay Somkuwar ◽  
Laxmi Kumre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Semiconductor Industry ◽  
Power Saving ◽  
Critical Issue ◽  
Leakage Power ◽  
Design Flow ◽  
Power Gating ◽  
Low Power Architectures

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

scholarly journals ASIC Implementation of DMA Controller

2016 ◽  
Vol 4 (1) ◽  
pp. 1-4
Author(s):  
Aman Agarwal ◽  
Arjun J Anil ◽  
Rahul Nair ◽  
K. Sivasankaran
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
System Performance ◽  
Direct Memory Access ◽  
Main Memory ◽  
Memory Access ◽  
Verilog Hdl ◽  
Peripheral Device ◽  
Power Constraints ◽  
System Memory

Direct Memory Access is a method of transferring data between peripherals and memory without using the CPU. It is designed to improve system performance by allowing external devices to directly transfer information from the system memory. We generally use asynchronous type of DMA as they respond directly to input. The DMA controller issues signals to the peripheral device and main memory to execute read and write commands. In this paper DMA controller was designed using Verilog HDL and simulated in Cadence NC Launch. The design was synthesized using low power constraints. Through this design we have decreased the power consumption to 69%.

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

2020 ◽  
Vol 12 ◽  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Ajay Kumar ◽  
Brahamdeo Prasad Singh
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Efficiency ◽  
Dynamic Logic ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage ◽  
Dynamic Circuits ◽  
Power Delay Product ◽  
Domino Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

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