Defect creation in the accumulation layer of a-Si: H thin-film transistors

1990 ◽  
Vol 61 (2) ◽  
pp. 251-261 ◽  
Author(s):  
N. Nickel ◽  
W. Fuhs ◽  
H. Mell
2006 ◽  
Vol 910 ◽  
Author(s):  
Andew Flewitt ◽  
Shufan Lin ◽  
William I Milne ◽  
Ralf B Wehrspohn ◽  
Martin J Powell

AbstractIt has been widely observed that thin film transistors (TFTs) incorporating an hydrogenated amorphous silicon (a-Si:H) channel exhibit a progressive shift in their threshold voltage with time upon application of a gate bias. This is attributed to the creation of metastable defects in the a-Si:H which can be removed by annealing the device at elevated temperatures with no bias applied to the gate, causing the threshold voltage to return to its original value. In this work, the defect creation and removal process has been investigated using both fully hydrogenated and fully deuterated amorphous silicon (a-Si:D) TFTs. In both cases, material was deposited by rf plasma enhanced chemical vapour deposition over a range of gas pressures to cover the a-g transition. The variation in threshold voltage as a function of gate bias stressing time, and annealing time with no gate bias, was measured. Using the thermalisation energy concept, it has been possible to quantitatively determine the distribution of energies required for defect creation and removal as well as the associated attempt-to-escape frequencies. The defect creation and removal process in a-Si:H is then discussed in the light of these results.


1995 ◽  
Vol 52 (7) ◽  
pp. 4680-4683 ◽  
Author(s):  
C. F. O. Graeff ◽  
M. S. Brandt ◽  
M. Stutzmann ◽  
M. J. Powell

2003 ◽  
Vol 93 (9) ◽  
pp. 5780-5788 ◽  
Author(s):  
R. B. Wehrspohn ◽  
M. J. Powell ◽  
S. C. Deane

1992 ◽  
Vol 284 ◽  
Author(s):  
I. J. Chung ◽  
C. H. Oh ◽  
W. Y. Kim ◽  
J. R. Hwang ◽  
Y. S. Kim ◽  
...  

ABSTRACTThe accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the threshold voltage shifts of a-Si TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the illumination periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.


2006 ◽  
Vol 910 ◽  
Author(s):  
Kwang-Sub Shin ◽  
Jae-Hoon Lee ◽  
Won-kyu Lee ◽  
Sang-Geun Park ◽  
Min-Koo Han

AbstractThe threshold voltage (VT) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the absence of a drain bias (VG=15V, VD=0V), the threshold voltage (VT) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (VG=15V, VD=20V), the VT shifts of asymmetric TFTs were less than symmetric TFT. The VT shifts of ‘L’ and ‘J’ shaped TFT were 0.29V, 0.24V respectively, while the VT shift of ‘I’ shaped TFT was 0.42V.The less VT degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less VT degradation compared with the symmetric TFT.


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