A new approach for digital calibration of timing-mismatch in four-channels time-interleaved analog-to-digital converters

2014 ◽  
Vol 9 (09) ◽  
pp. T09001-T09001 ◽  
Author(s):  
E Majdinasab ◽  
E Farshidi
Keyword(s):  
Analog To Digital Converters ◽  
Digital Calibration ◽  
New Approach ◽  
Analog To Digital ◽  
Time Interleaved

All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters

2017 ◽  
Vol 25 (9) ◽  
pp. 2552-2560 ◽  
Author(s):  
Shuai Chen ◽  
Luke Wang ◽  
Hong Zhang ◽  
Rosanah Murugesu ◽  
Dustin Dunwell ◽  
...  
Keyword(s):  
Analog To Digital Converters ◽  
Digital Calibration ◽  
Mismatch Error ◽  
Analog To Digital ◽  
Time Interleaved

A LOW-POWER DIGITAL CALIBRATION OF SAMPLING TIME MISMATCHES IN TIME-INTERLEAVED A/D CONVERTERS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450115
Author(s):  
MOHAMMAD NIABOLI-GUILANI ◽  
AMIR BAZRAFSHAN-JORSHARI ◽  
REZA MESHKIN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Calibration ◽  
Low Power Consumption ◽  
New Approach ◽  
Analog To Digital ◽  
Timing Errors ◽  
Approach Method ◽  
Foreground Calibration ◽  
Time Interleaved

This paper presents, a novel digital foreground calibration technique in order to reduce the effects of timing-skew in time-interleaved analog-to-digital converters (ADCs). The proposed technique implementation is simple and helps to achieve very low power consumption. This technique is based on the using of a simple reference comparator which is synchronized by one of sub-channels in each cycle of calibration. Also the detection and correction are implemented by a simple LMS loop that guarantee the convergence of algorithm. Finally, simulation results show that the new approach method can effectively correct timing errors for a specified input signal, and achieves a low power consumption, low computational complexity and high convergence speed and also verify theoretical equations for it.

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters

2019 ◽  
Vol 28 (06) ◽  
pp. 1950090
Author(s):  
Jian Luo ◽  
Jing Li ◽  
Shuangyi Wu ◽  
Ning Ning ◽  
Yang Liu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Dynamic Range ◽  
Optimization Technique ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Limited Bandwidth ◽  
Behavior Simulation ◽  
Calibration Methods ◽  
Time Interleaved ◽  
Sampling Sequences

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

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