scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

2019 ◽  
Vol 16 (1) ◽  
pp. 21-27
Author(s):  
Wei-Wei Liu (Xenia) ◽  
Berdy Weng ◽  
Jerry Li ◽  
Cing-Kun Yeh

Abstract The Kirkendall void (KV) has been a well-known issue for long term reliability of semiconductor interconnects. KVs exist at the interfaces of Cu and Sn and the growing intermetallic compound (IMC) Cu6Sn5 at the initial stage, and a part of the IMC is converted to Cu3Sn when the environmental stress added. In this article, all the assembled packages pass the condition of unbiased long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high-temperature storage. A large numbers of KVs was observed after 200 cycles of temperature cycling. Various assembly structures were monitored, and various IMC thicknesses were concluded to be functions of stress test. Cu3Sn, Ni3Sn4, and Cu6Sn5 are not significantly affected by heat, but Ni3Sn4 grows steadily.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000129-000134
Author(s):  
Wei-Wei Liu (Xenia) ◽  
Berdy Weng ◽  
Jerry Li ◽  
CK Yeh

Abstract The kirkendall void had been a well-known issue for long term reliability of semiconductor interconnects, while even the KVs existing at the interfaces of Cu & Sn, it may still be able to pass the condition of un-bias long term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000hrs of high temperature storage. A large numbers of KVs was observed after 200cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 & Cu layers. These kinds of voids will growth proportional with the aging time at initial stage, but slowing down attribute to the barrier layer of Cu3Sn & Cu interfaces. This paper compare various IMC thickness as a function of stress test, the Cu3Sn & Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture.


Author(s):  
Klaus Peter Tschernay ◽  
Thomas Haber

Abstract In today’s supply chains based on complex division of labor qualification plans must be executed at various levels of semifinished products. This study shows how a supporting process, assumed to be uncritical in terms of the qualification scope for a bare silicon die, is responsible for qualification fails. Although such failures are not relevant for the quality of the final product careful and thorough analysis is required to invalidate such failure modes.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.


Author(s):  
Zheng Wang ◽  
zhen Ma ◽  
Xiongfeng Hu ◽  
Ruirui Zhao ◽  
Junmin Nan

Abstract Mathematical models to evaluate and predict the performance degradation of lithium-ion batteries (LIBs) with different status of charge (SOC) in long-term high-temperature storage which are also applicable for setting rational storage conditions (temperature, SOC, and time) of LIBs were established. Parameters including voltage drop (Delta V), reversible capacity (RC) loss, and internal impedance (IMP) increase of LIBs under different temperature (60, 45, and 25°C) are used to allow the model to clarify its function. According to the results obtained from commercial 18650 cylindrical batteries with LiNi0.33Co0.33Mn0.33O2 cathode, the mathematical relationship between Delta V and storage days (x) is fitted into a simple formula: Delta V =m.In(x)-n, and similarly, RC loss = m'.exp (n'.x) and IMP increase = m''.xn'' can also be acquired. In these formulas, m, n, m', n', m'' and n'' are constants when temperature and SOC are fixed. If only the temperature is fixed, the value of these constants can be derived into a function with SOC (y), respectively, while further plugging the function into the calculation formula of Delta V, RC loss, and IMP increase, respectively, allows the mathematical models to be set up.


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