300°C Optical Communications

A high temperature optical link capable of multi-megabits per second data rates at 300°C is presented. The system utilizes wide bandgap optical sources and detectors to achieve extreme temperature operation. Testing was conducted at multiple temperatures between room temperature and 325°C and at multiple light source currents. Light coupling into and out of a UV capable optical fiber was evaluated, and a model was created utilizing the test data of the photodiode dark current and the fiber optic cable insertion loss and attenuation and assess optical communications capability to 325°C and beyond.

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/− 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

Simulating the Effect of Rigid Frameworks on the Mechanical Properties of Transient Liquid Phase Sintered (TLPS) Alloys

The need for power electronic devices and materials that can operate in harsh environments, together with the Restriction of Hazardous Substances (RoHS) legislation, has driven industry and researchers to develop new attach materials. Transient Liquid Phase Sintered (TLPS) joints are strong candidates to replace the current die attach materials due to their superior mechanical, thermal, and electrical properties. Despite these qualities, current TLPS systems may exhibit stiff and brittle behavior that can lead to die or attach fracture under large thermomechanical strains during wide temperature range cycling, or under mechanical stress from shock and vibration loading, such as is experienced in automotive electronics. This paper presents an approach for reducing thermal and mechanical strain levels by incorporating Transmission Electron Microscopy (TEM) Cu grids as a reinforcement to the attach material. The grids serve as ductile reinforcement capable of absorbing elastic and plastic energy, and as a barrier for crack propagations through the relative brittle TLPS material. Homogenization calculations were used to evaluate the effective properties of the TLPS, followed by numerical analysis that shows the effect of the grids on the die attach structure, and the mechanical integrity of the design.

470 Celsius Packaging System for Silicon Carbide Electronics

High temperature Silicon Carbide (SiC) integrated circuit (IC) processes have enabled devices that operate at >450°C for more than a year. These results have established the need for more advanced and practical packaging strategies. Off the shelf state of the art packages cannot withstand the same high temperatures as the semiconductor can for long periods of time. Packaging SiC die to survive temperatures >450°C, while also maintaining a reasonable packaging strategy that is agile, rapid, and modular, presents new challenges. Presented is a technique for packaging SiC die with a focus on additive manufacturing, modular design scaling, and rugged survivability. This packaging strategy utilizes state of the art Additive Manufacturing (AM) methods, using an nScrypt 3Dn-Tabletop printer, together with stereolithography (SLA) digital light processing (DLP) 3D printing. Ultra-violet (UV) curable ceramic resins are used to create high temperature connectors. A design environment is also described, in which first time correct, interconnect layers are verified in software to reduce the risk of errors. A Ceramic Wiring Board Process Design Kit (CWBPDK) allows the design of single or multiple layers of metal, with fabricated SiC die. This interconnect is verified with standard design rule checking (DRC) and layout vs. schematic (LVS) software. Entire systems in packages can be verified using multiple SiC die. Input and output pins (I/O) are connected to these modules using metal connectors. After design, manufacturing can be performed in just a few days. A system in package for driving a stepper motor was designed and fabricated using this packaging method. The motor actuator design utilizes four separate SiC die. These die contain large JFETs designed for sourcing current in a unipolar stepper motor architecture. This module was placed in a furnace at 470°C and demonstrated functional operation for over 1000 hours. These devices were able to source an average of 30 mA in >400°C temperatures to drive the room temperature stepper motor. A high I/O count, next generation package for discrete SiC chips was also designed using this packaging system. A single large JFET component was soaked for over 100 hours at both 500°C and 800°C. Utilizing Ozark IC’s automated test design environment, several DC and transient variables were captured for both tests and will be presented.

A 300°C High Reliability HALT/HAST Screening/Sorting Procedure for Ceramic Capacitors – Part 2

This is Part 2 of a study initially presented at HiTEC 2018, for context, some introductory material is duplicated. A highly accelerated life test (HALT) and highly accelerated stress test (HAST) procedure for ceramic capacitors developed by the author in the mid 1980’s to early 1990’s, and published in 1994, consists of a 400 Volt biased six (6) hour stress sort at 150°C (423K), a methanol current leakage test that located mechanical and structural cracks, a visual inspection at ten times (10X) magnification, and a capacitance and dissipation measurement before and after the test. In over thirty (30) years of use, there has never been a user reported in-circuit failure in industrial, military, and aerospace application at temperatures as high as 500°C (773K). However, reviewing user feedback, two concerns with the original sorting procedure are the stress is performed at 150°C (423K), and the lack of a more detailed ceramic capacitor electrical model. To address the first, the low aging temperature, the stress temperature was increased from 150°C to 300°C, in order to age ceramic solid state crystal mineral phases that may change with temperature. The test results for X7R and NP0/COG multilayer ceramic capacitors (MLCC) at 300°C, are compared to the test results using the original HALT/HAST procedure at 150°C. Differences between X7R/NP0/COG and porcelain capacitors are discussed when applicable. Further, a more detailed ceramic capacitor electrical model that represents the physical and electrical characteristics of the ceramic capacitors is presented, including the electrical current leakage effects with temperature, and the carbonized residue effects from the manufacturing process.

Low Loss LTCC Ag System for 5G Applications

Low dielectric constant/low loss LTCC materials have drawn much attention with the emergence of 5G wireless telecommunications. LTCC offers unique properties in the millimeter wave frequency range. The low dielectric constant and dielectric loss enable low latency devices with enhanced performance. To meet the market demands of higher performance and lower cost, Ferro has developed a new M7 LTCC/Ag cofireable system suitable for antenna in 5G and other high frequency applications. M7 LTCC ceramic green tape and cofireable Ag conductors have been developed and tested. Properties of the LTCC/Ag system are included herein including high frequency dielectric properties.

Package Design and Analysis for Vertical Gallium Nitride Field Effect Transistors

Gallium nitride (GaN) is a wide band gap semi-conductor with superior electron mobility to silicon carbide. These properties allow for the design of high temperature capable devices with excellent on resistance and breakdown voltage for their size. However, bulk GaN is difficult to fabricate and doping for field effect transistor (FET) control has been elusive, so vertical GaN devices are not commonplace. This paper measures the characteristics of vertical GaN FETs in the development stage and discusses packaging them for fabrication feedback and for future high temperature aplications.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300 °C

Sensors are key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow a reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project ‘eHarsh’ to overcome this hurdle. In the course of the project an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high temperature 0.35 micron SOI-CMOS technology focusing operating temperatures up to 300 °C. The chipset is assembled on a multilayer ceramic LTCC-board using flip chip technology. The ceramic board consists of 4 layers with a total thickness of approx. 0.9 mm. The internal wiring is based on silver paste while external contacts were alternatively manufactured in silver (sintering/soldering) or in gold-alloys (wire bonding). As interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high quality flip chip interconnects can be generated.