Enhanced Failure Analysis (FA) of Organic Contamination Using Submicron Simultaneous IR and Raman Spectroscopy: Breakthrough Developments of Optical Photothermal IR (O-PTIR)

Rapid identification of organic contamination in the semi and semi related industry is a major concern for research and manufacturing. Organic contamination can affect a system or subsystem’s performance and cause premature failure of the product. As an example, in February 2019 the Taiwan Semiconductor Manufacturing Company (TMSC), a major semiconductor manufacturer, reported that a photoresist it used included a specific element which was abnormally treated, creating a foreign polymer in the photoresist resulting in an estimated loss of $550M [1].

Short Wavelength Probing for Fault Isolation Applications

Short wavelength probing (SWP) uses wavelengths of light shorter than 1100 nm or energies higher than silicon bandgap for laser probing applications. While SWP allows a significant improvement to spatial resolution, there are aberrations to the collected laser probing waveforms which result in difficulties in signal interpretations. In this work, we assess the signals collected through SWP (785 nm) and introduce a photodiode model to explain the observations. We also present a successful case study using 785 nm for failure analysis in sub-20 nm FinFET technology.

Fault Isolation of Metal-Insulator-Metal (MiM) Capacitor Failures by Lock-in Thermography (LIT)

The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.

FinFET Transistor Output Drive Performance Modification by Focused Ion Beam (FIB) Chip Circuit Editing

Focused Ion Beam (FIB) chip circuit editing is a well-established highly specialized laboratory technique for making direct changes to the functionality of integrated circuits. A precisely tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, create functional changes in devices or the copper wiring pattern, and reseals the chip surface. When executed within reasonable limits, the revised circuit logic functions essentially the same as if the changes were instead made to the photomasks used to fabricate the chip. The results of the intended revision, however, can be obtained weeks or months earlier than by a full fabrication run. Evaluating proposed changes through FIB modification rather than proceeding immediately to mask changes has become an integral part of the process for bringing advanced designs to market at many companies. The end product of the FIB process is the very essence of handcrafted prototyping. The efficacy of the FIB technique faces new challenges with every generation of fabrication process node advancement. Ever shrinking geometries and new material sets have always been a given as transistor size decreases and overall packing density increases. The biggest fundamental change in recent years was the introduction of the FinFET as a replacement for the venerable planar transistor. Point to point wiring change methodology has generally followed process scaling, but transistor deletions or modifications with the change to Fins require a somewhat different approach and much more careful control due to the drastic change in height and shape. We also had to take into consideration the importance of the 4th terminal, the body-tie, that is often lost in backside editing. Some designs and FET technology can function acceptably well when individual devices are no longer connected to the bulk substrate or well, while others can suffer from profound shifts in performance. All this presents a challenge given that the primary beam technology improvements of the fully configured chip edit FIB has only evolved incrementally during the same time period. The gallium column system appears to be reaching its maximum potential. Further, as gallium is a p-type metal dopant, there are limitations to its use in close proximity to certain active semiconductor devices. Amorphous material formation and other damage mechanisms that extend beyond what can be seen visually when endpointing must also be taken into account [1]. Device switching performance and even transmission line characteristics of nearby wiring levels can be impacted by material structural changes from implantation cascades. Last year our lab participated in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over/around them is commonly done, but modifications to the physical size of an FET device is a rare request and generally not attempted. It requires a level of precision in beam control and post-edit treatment that can be difficult to execute cleanly. Once again during a complex edit task we considered the use of an alternate ion beam species such as neon, or reducing the beam energy (low kV) on the gallium tool. Unfortunately, we don’t yet have easy access to a versatile viable replacement column technology grafted to a fully configured edit station. And while there should be significantly reduced implant damage and transistor functional change when a gallium column FIB is operated at lower accelerating potential [2], the further loss of visual acuity due to the reduced secondary emission, especially when combined with ultra-low beam currents, made fast and accurate navigation near impossible. We instead chose the somewhat unconventional approach of using an ultra-low voltage electron beam to do much of the navigation and surface marking prior to making the final edits with the gallium ion beam in a dual-beam FIB tool. Once we had resolved how to accurately navigate to the transistors in question and expose half of the structure without disturbing the body-tie, we were able to execute the required cut to trim away 50% of the structure and reduce the effective drive. Several of the FIB modified units functioned per the design parameters of a smaller sized device, giving confidence to proceed with the revised mask set. To our surprise, the gallium beam performed commendably well in this most difficult task. While we still believe that an inert beam of similar characteristics would be preferable, this work indicates that gallium columns are still viable at the 14 nm FinFET node for even the most rigorous of editing requirements. It also showed that careful application of e-beam imaging on the exposed underside of FinFET devices could be performed without degrading or destroying them.

Cutting-Edge Sample Preparation from FIB to Ar Concentrated Ion Beam Milling of Advanced Semiconductor Devices

Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.

Yield and Failure Analysis of FinFET Source to Drain Leakage in 12nm Technology

Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

A Minor Change in Sample Preparation Leads to Unexpected Qualification Fails During High Temperature Storage Stress Test

In today’s supply chains based on complex division of labor qualification plans must be executed at various levels of semifinished products. This study shows how a supporting process, assumed to be uncritical in terms of the qualification scope for a bare silicon die, is responsible for qualification fails. Although such failures are not relevant for the quality of the final product careful and thorough analysis is required to invalidate such failure modes.

Automated Sample Depth Targeting with Low kV Cleaning by Focused Ion Beam Microscopy for Atom Probe Tomography

Focused ion beam (FIB) microscopy is an essential technique for the site-specific sample preparation of atom probe tomography (APT). The site specific APT and automated APT sample preparation by FIB have allowed increased APT sample volume. In the workflow of APT sampling, it is very critical to control depth of the sample where exact region of interest (ROI) for accurate APT analysis. Very precise depth control is required at low kV cleaning process in order to remove the damaged layer by previous high kV FIB process steps. We found low kV cleaning process with 5 kV and followed by 2kV beam conditions delivers better control to reached exact ROI on Z direction. This understanding is key to make APT sample with fully automated fashion.

A Novel Deprocessing Technique for Revealing Transistor-Level Damage on 7nm FinFET Devices

Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

LASRE: A Novel Approach to Large area Accelerated Segmentation for Reverse Engineering on SEM images

In the hardware assurance community, Reverse Engineering (RE) is considered a key tool and asset in ensuring the security and reliability of Integrated Circuits (IC). However, with the introduction of advanced node technologies, the application of RE to ICs is turning into a daunting task. This is amplified by the challenges introduced by the imaging modalities such as the Scanning Electron Microscope (SEM) used in acquiring images of ICs. One such challenge is the lack of understanding of the influence of noise in the imaging modality along with its detrimental effect on the quality of images and the overall time frame required for imaging the IC. In this paper, we characterize some aspects of the noise in the image along with its primary source. Furthermore, we use this understanding to propose a novel texture-based segmentation algorithm for SEM images called LASRE. The proposed approach is unsupervised, model-free, robust to the presence of noise and can be applied to all layers of the IC with consistent results. Finally, the results from a comparison study is reported, and the issues associated with the approach are discussed in detail. The approach consistently achieved over 86% accuracy in segmenting various layers in the IC.