Effect of High Temperature Storage and Harden Accelerated Storage Test on Reliability of Flip Chip Bumps

Author(s):  
Zhizhe Wang ◽  
Bin Wang ◽  
Shuai Zhou ◽  
Yu Sun ◽  
Xiaoqiang Wang ◽  
...  
2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.


Author(s):  
Chu-Chung Lee ◽  
TuAnh Tran ◽  
Varughese Mathew ◽  
Rusli Ibrahim ◽  
Poh-Leng Eu

Since 2008, fine gauge (≤ 35 μm diameter) copper (Cu) wire has been rapidly replacing fine gauge gold (Au) wire in consumer, commercial, and industrial products [2–4]. The first wave of Cu wire products used bare, uncoated Cu wire which is soon to known having Cu-Al IMC corrosion induced by mobile chlorine ions in the epoxy mold compound system when IC parts are subjected to moisture related package stress tests such as biased HAST (Highly Accelerated Stress Test) [1–7]. Additionally, when comparing to Au wires, the 2nd bond process window of bare Cu wire can be very narrow and becomes a concern of moving into HVM (high volume manufacturing) [8]. Thus, palladium-coated Cu (PdCu) wire was introduced to the semiconductor assembly market aiming to provide more margin of passing biased HAST and enhance 2nd bond process capability [9–13]. However, the use of Pd-Cu wire is not a panacea to all Cu wire bond problems. One unique anomaly for Pd-Cu wire is the Cu ball void [1] which is observed only with Pd-Cu and not bare Cu ball bonds during HTSL (high temperature storage life) tests. The mechanism of forming Cu ball voids was proven to be the galvanized corrosion mechanism with Pd-Cu coupling. Significant factors affecting the formation rate of Cu ball voids are found to be baking temperature, EFO current settings, bonding parameters and mold compound additives (sulfur). Both anodic and cathodic chemical reactions will be proposed for Cu voids in this paper. Even though Cu void can be considered as a cosmetic defect for the majority of application since the peak temperature of device mission profile is always no larger than 175C. The application at extreme high temperature (for example, 190C) can actually cause electrical failure at the ball bon region due to the Cu void formation in terms of size and location at the Cu-Al IMC region. The main effect is due to the selected mold compound having high amount of metallic adhesion promoter which is sulfur-based and extensive high temperature storage test condition (190C). The FIB/SEM picture of failing ball bond due to Cu voids from this particular device will be presented in the paper. Thus, a newly developed doped Cu wire without Pd coating has been proposed by many wire suppliers to overcome Cu ball voids. However, doped Cu wires without Pd coating have suffered the same high volume manufacturing issues observed by bare Cu wires. For example, short tail and mean time between assist (MTBA) for doped Cu wires without Pd coating are both as poor as bare Cu wires. We will present high temperature storage test results obtained by doped PdCu wires in this paper. To balance high volume manufacturing issues and Cu void formation, doped PdCu wires are also proposed recently. Several doped PdCu wires whose extensive high temperature storage results (220C) will be presented in this paper. The worst case mold compound with high amount of sulfur based adhesion promoter has been used to test the effectiveness of these new wire types. At such harsh testing condition, there is one doped PdCu wire in our test can actually survive without electrical failed ball bond due to Cu voids. Factors of effectiveness of doped PdCu wires will be discussed in this paper. Authors have chosen to focus on Cu voids at both 1st bond (ball bond) and 2nd bond (wedge). 20 um wire diameter has been used for all test vehicle in this study. All controlling factors of eliminating Cu voids will surely be included at the end of this paper.


2013 ◽  
Vol 740-742 ◽  
pp. 669-672 ◽  
Author(s):  
Toru Izumi ◽  
Tetsuro Hemmi ◽  
Toshihiko Hayashi ◽  
Katsunori Asano

The reliability of three kinds of high heat-resistant resins has been evaluated under high temperatures. These resins were applied to insulation substrates and a high temperature storage test has been carried out. The insulation performance of the resins was evaluated by applying 20 kV between a pair of electrodes on the substrate covered with resin. The insulation performance at 20 kV was maintained in samples with two of the three kinds of resins for 1,000 hours at 225oC. In a higher temperature storage test at 250oC, samples with one of the kinds of resin were not able to maintain insulation of 20 kV for 200 hours, while the two remaining resins were not able to maintain the insulation for 1,000 hours. In most samples that were not able to maintain the insulation, cracks or detachments were seen. Hardening caused by oxidation of the resin and differences in the coefficient of linear thermal expansion (CTE) are considered as causes of the cracks or detachments. It is thought to be necessary to lower the CTE of the resin and inhibit its oxidation in order to use it at more than 250oC for long periods of time.


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