In this article, a design of multi-channel data acquisition system is presented. With FPGA as the core controller, the system can implement logic control over the high-speed ADC and acquire high-speed and high-resolution sample data. Using asynchronous FIFO as a cache, it can transfer data between two different clock domains: ADC data acquisition module and RS485 data module, which helps to improve the work efficiency and data throughput of the system. In the Quartus II development platform, Verilog hardware description language is adopted and finite state machine so that parallel acquisition operation to multi-channel ADC controlled by FPGA can be achieved and the system can become equipped with high-resolution, strong real-timeliness, low noise interference and other advantages. When it comes to the final step, simulation of AD sampling, asynchronous FIFO and RS485 transmission are conducted under the Modelsim environment and on-line testing by Signaltap to the system is synchronously implemented. The validity and reliability of the system are verified.