A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156405003260 ◽

2005 ◽

Vol 15 (02) ◽

pp. 459-476

Author(s):

C. PATRICK YUE ◽

JAEJIN PARK ◽

RUIFENG SUN ◽

L. RICK CARLEY ◽

FRANK O'MAHONY

Keyword(s):

Low Power ◽

Electromagnetic Interference ◽

Continuous Time ◽

High Speed ◽

High Performance ◽

Process Variations ◽

Cmos Process ◽

Power Circuit ◽

Crosstalk Cancellation ◽

Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

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A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

Journal of Circuits System and Computers ◽

10.1142/s0218126613400331 ◽

2013 ◽

Vol 22 (10) ◽

pp. 1340033 ◽

Cited By ~ 2

Author(s):

HONGLIANG ZHAO ◽

YIQIANG ZHAO ◽

YIWEI SONG ◽

JUN LIAO ◽

JUNFENG GENG

Keyword(s):

Power Consumption ◽

Low Power ◽

Integrated Circuit ◽

High Performance ◽

Supply Voltage ◽

Cmos Technology ◽

High Gain ◽

Readout Integrated Circuit ◽

Chip Area ◽

Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

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A High Uniformity Readout Integrated Circuit for Infrared Focal Plane Array Applications

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.602-605.2632 ◽

2014 ◽

Vol 602-605 ◽

pp. 2632-2636

Author(s):

Tong Zhou ◽

Tao Dong ◽

Yan Su ◽

Yong He

Keyword(s):

Integrated Circuit ◽

Focal Plane ◽

Infrared Image ◽

Low Frequency ◽

Low Noise ◽

Focal Plane Arrays ◽

Cmos Process ◽

Readout Integrated Circuit ◽

Practical Applications ◽

High Uniformity

Infrared focal plane arrays (IRFPA) suffer from inherent low frequency and fixed patter noise (FPN). To achieve high quality infrared image by mitigating the FPN of IRFPAs, a novel low-noise and high uniformity readout integrated circuit (ROIC) has been proposed. A correlated double sampling (CDS) with single capacitor method has been adopted in the ROIC design which can effectively reduce the FPN, KTC and 1/f noise. A 4×4 experimental readout chip has been designed and fabricated using the SMIC 0.18 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the proposed ROIC has a good performance in practical applications.

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Fast 3D Integrated Circuit Placement Methodology using Merging Technique

Defence Science Journal ◽

10.14429/dsj.69.14410 ◽

2019 ◽

Vol 69 (3) ◽

pp. 217-222 ◽

Cited By ~ 1

Author(s):

Srinivas Sabbavarapu ◽

Amit Acharyya ◽

P. Balasubramanian ◽

C. Ramesh Reddy

Keyword(s):

Form Factor ◽

Low Power ◽

Integrated Circuit ◽

High Speed ◽

High Performance ◽

Three Dimensional ◽

Heterogeneous Systems ◽

Reduced Form ◽

Wire Length ◽

Ic Design

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

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