3D EXIT Charts for Analyzing the 5G 3GPP New Radio LDPC Decoder

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

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A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid49098.2020.00018 ◽

2020 ◽

Cited By ~ 1

Author(s):

Anuj Verma ◽

Rahul Shrestha

Keyword(s):

Vlsi Architecture ◽

Ldpc Decoder ◽

New Radio

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A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9181188 ◽

2020 ◽

Author(s):

Anuj Verma ◽

Rahul Shrestha

Keyword(s):

Wireless Communication ◽

Vlsi Architecture ◽

Next Generation ◽

Ldpc Decoder ◽

New Radio ◽

Communication Standard

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A High-Throughput LDPC Decoder Based on GPUs for 5G New Radio

2020 IEEE Symposium on Computers and Communications (ISCC) ◽

10.1109/iscc50000.2020.9219558 ◽

2020 ◽

Author(s):

Rongchun Li ◽

Xin Zhou ◽

Hengyue Pan ◽

Huayou Su ◽

Yong Dou

Keyword(s):

High Throughput ◽

Ldpc Decoder ◽

New Radio

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Reduced-complexity offset min-sum check node unit for layered 5G LDPC decoder

Telfor Journal ◽

10.5937/telfor2101007p ◽

2021 ◽

Vol 13 (1) ◽

pp. 7-12

Author(s):

Vladimir Petrović ◽

Mezeni El

Keyword(s):

Parity Check ◽

Ldpc Decoder ◽

Low Density Parity Check ◽

Novel Approach ◽

New Radio ◽

Variable Weight ◽

Decoder Architecture ◽

Check Node ◽

Higher Weights ◽

Reduced Complexity

This paper presents a novel approach for the reduced-complexity Min-Sum (MS) decoding of low density parity check (LDPC) codes in the partially parallel layered decoder architecture, which contains a large number of serial check node processors. Reduced complexity is obtained by using the variant of the single-minimum Offset Min-Sum (smOMS) algorithm that approximates a second minimum with the addition of the variable weight parameter to the minimum value. Although the reduced-complexity MS algorithms primarily reduce hardware resources in fully parallel implementations, the results showed that a considerable reduction can be obtained if serial check node processors are used. The paper also proposes a better subminimum estimation for irregular codes from 5G new radio (5G NR). The method uses smaller subminimum estimation weights in check nodes with a higher degree and higher weights in check nodes with a smaller degree, which leads to the significant improvement in the SNR performance. Additionally, it is shown that SNR performance can be further improved by applying offset before minimum calculation, which differs from conventional Min-Sum approaches.

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Electromagnetic earth environment: new radio diagnostic

IET 11th International Conference on Ionospheric Radio Systems and Techniques (IRST 2009) ◽

10.1049/cp.2009.0078 ◽

2009 ◽

Author(s):

H. Rothkaehl ◽

B. Thide ◽

J.E. Bergman

Keyword(s):

New Radio ◽

Earth Environment

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5G New Radio: Waveform, Frame Structure, Multiple Access, and Initial Access

IEEE Communications Magazine ◽

10.1109/mcom.2017.1601107 ◽

2017 ◽

Vol 55 (6) ◽

pp. 64-71 ◽

Cited By ~ 144

Author(s):

Shao-Yu Lien ◽

Shin-Lin Shieh ◽

Yenming Huang ◽

Borching Su ◽

Yung-Lin Hsu ◽

...

Keyword(s):

Multiple Access ◽

Frame Structure ◽

New Radio

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Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽

10.3390/electronics10091106 ◽

2021 ◽

Vol 10 (9) ◽

pp. 1106

Author(s):

Vladimir L. Petrović ◽

Dragomir M. El Mezeni ◽

Andreja Radošević

Keyword(s):

Channel Coding ◽

Parallel Architecture ◽

Ldpc Codes ◽

Parity Check ◽

Case Scenario ◽

New Radio ◽

Physical Channel ◽

Computationally Intensive ◽

Hardware Processing ◽

Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

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