A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio

2020 ◽  
Author(s):  
Anuj Verma ◽  
Rahul Shrestha
Keyword(s):  
Vlsi Architecture ◽  
Ldpc Decoder ◽  
New Radio

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

scholarly journals Implementation of Layered Decoding Architecture for LDPC Code using Layered Min-Sum Algorithm

2017 ◽  
Vol 18 (2) ◽  
pp. 128-136
Author(s):  
Sandeep Kakde ◽  
Atish Khobragade ◽  
Shrikant Ambatkar ◽  
Pranay Nandanwar
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Vlsi Architecture ◽  
Ldpc Code ◽  
Error Performance ◽  
Ldpc Decoder ◽  
Parallel Design ◽  
Modulation Techniques ◽  
Better Than ◽  
Bpsk Modulation

For binary field and long code lengths, Low Density Parity Check (LDPC) code approaches Shannon limit performance. LDPC codes provide remarkable error correction performance and therefore enlarge the design space for communication systems.In this paper, we have compare different digital modulation techniques and found that BPSK modulation technique is better than other modulation techniques in terms of BER. It also gives error performance of LDPC decoder over AWGN channel using Min-Sum algorithm. VLSI Architecture is proposed which uses the value re-use property of min-sum algorithm and gives high throughput. The proposed work has been implemented and tested on Xilinx Virtex 5 FPGA. The MATLAB result of LDPC decoder for low bit error rate (BER) gives bit error rate in the range of 10-1 to 10-3.5 at SNR=1 to 2 for 20 no of iterations. So it gives good bit error rate performance. The latency of the parallel design of LDPC decoder has also reduced. It has accomplished 141.22 MHz maximum frequency and throughput of 2.02 Gbps while consuming less area of the design.

scholarly journals 3D EXIT Charts for Analyzing the 5G 3GPP New Radio LDPC Decoder

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 188797-188812
Author(s):  
Shuai Shao ◽  
Yangyishi Zhang ◽  
Robert G. Maunder ◽  
Lajos Hanzo
Keyword(s):  
Ldpc Decoder ◽  
New Radio ◽  
Exit Charts

A High-Throughput LDPC Decoder Based on GPUs for 5G New Radio

2020 ◽  
Author(s):  
Rongchun Li ◽  
Xin Zhou ◽  
Hengyue Pan ◽  
Huayou Su ◽  
Yong Dou
Keyword(s):  
High Throughput ◽  
Ldpc Decoder ◽  
New Radio

scholarly journals Reduced-complexity offset min-sum check node unit for layered 5G LDPC decoder

2021 ◽  
Vol 13 (1) ◽  
pp. 7-12
Author(s):  
Vladimir Petrović ◽  
Mezeni El
Keyword(s):  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Novel Approach ◽  
New Radio ◽  
Variable Weight ◽  
Decoder Architecture ◽  
Check Node ◽  
Higher Weights ◽  
Reduced Complexity

This paper presents a novel approach for the reduced-complexity Min-Sum (MS) decoding of low density parity check (LDPC) codes in the partially parallel layered decoder architecture, which contains a large number of serial check node processors. Reduced complexity is obtained by using the variant of the single-minimum Offset Min-Sum (smOMS) algorithm that approximates a second minimum with the addition of the variable weight parameter to the minimum value. Although the reduced-complexity MS algorithms primarily reduce hardware resources in fully parallel implementations, the results showed that a considerable reduction can be obtained if serial check node processors are used. The paper also proposes a better subminimum estimation for irregular codes from 5G new radio (5G NR). The method uses smaller subminimum estimation weights in check nodes with a higher degree and higher weights in check nodes with a smaller degree, which leads to the significant improvement in the SNR performance. Additionally, it is shown that SNR performance can be further improved by applying offset before minimum calculation, which differs from conventional Min-Sum approaches.

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