Design of Low Power Low Input Impedance CMOS Current Comparator

Author(s):  
Rockey Choudhary ◽  
Monika Bhardwaj ◽  
B.P. Singh ◽  
Kopal Gupta
Author(s):  
Arnold C. Paglinawan ◽  
Charmaine C. Paglinawan ◽  
Shao-Chun Cheng ◽  
Wen-Yaw Chung

2008 ◽  
Vol 17 (06) ◽  
pp. 1139-1149 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
SURACHET KHUCHAROENSIN

In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.


2010 ◽  
Vol 66 (1) ◽  
pp. 9-18 ◽  
Author(s):  
Hassan Faraji Baghtash ◽  
Seyed Javad Azhari

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