Phase error compensation method for the characterisation of low-power-factor inductors under high-frequency large-signal excitation

Author(s):  
W. Chen ◽  
L.M. Ye ◽  
D.Y. Chen ◽  
F.C. Lee
Optik ◽  
2019 ◽  
Vol 178 ◽  
pp. 830-840
Author(s):  
Shuai Wang ◽  
Maosheng Xiang ◽  
Bingnan Wang ◽  
Fubo Zhang ◽  
Yirong Wu

2012 ◽  
Vol 59 (8) ◽  
pp. 1706-1719 ◽  
Author(s):  
Ja-Yol Lee ◽  
Mi-Jeong Park ◽  
Byung-Hun Min ◽  
Seongdo Kim ◽  
Mun-Yang Park ◽  
...  

Author(s):  
Ja-Yol Lee ◽  
Mi-Jeong Park ◽  
Byonghoon Mhin ◽  
Seong-Do Kim ◽  
Moon-Yang Park ◽  
...  

2021 ◽  
Vol 2015 (1) ◽  
pp. 012065
Author(s):  
V V Kirillov ◽  
P A Turalchuk

Abstract A phase compensation method for 1-bit phase quantized transmitarray is discussed. Using the tiled architecture of the transmitarray, the position of each unit cell is changed along the optical axis of the transmitarray. The spatial displacement allows changing the resulting phase distribution along the transmitarray aperture. Analytical calculations were performed to demonstrate the performance of the transmitarray radiation pattern.


Author(s):  
Chuangze Li ◽  
Benguang Han ◽  
Jie He ◽  
Longsheng Wu

Aiming at the requirement of high speed and precision, low-power and large-capacity load of serial data interface for aerospace super large array(15k×15k) CMOS image sensor, a design scheme low voltage differential signal (LVDS) driver by combining the split-length method with the pre-emphasis technique is proposed. Firstly, comparing with the general design schemes, the present scheme uses the split-length compensation method to increase effectively the unity-gain bandwidth while keeping the op-amp gain constant. Secondly, the pre-emphasis technique is used to compensate the LVDS driver for high-frequency components to improve the driving capability of the capacitive load and high speed signal integrity (SI). The simulation results show that the accuracy of the common-mode feedback voltage is improved by using the split-length compensation method, and also the common-mode voltage changes below 15 mV. The pre-emphasis technique is used to enhance the amplitude of the high-frequency components lost during the high-speed transmission. The quality of the signal eye diagram during high-speed transmission reduces the bit error rate, and both the transmission rate and the driving load capacity are two times more than the general design (1.2 Gb/s@12 pF), and the quiescent current consumption is only 4.6 mA@12 pF. The present LVDS driver design is implemented in a typical CMOS process of 0.18 μm.


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