FPGA based Digital Pulse Width Modulator with Time Resolution under 2 ns

Author(s):  
Santa C. Huerta ◽  
A. de Castro ◽  
O. Garcia ◽  
J.A. Cobos
2013 ◽  
Vol 28 (10) ◽  
pp. 4466-4472 ◽  
Author(s):  
Daniel Costinett ◽  
Miguel Rodriguez ◽  
Dragan Maksimovic

2014 ◽  
Vol 12 ◽  
pp. 91-94 ◽  
Author(s):  
M. Weber ◽  
T. Vennemann ◽  
W. Mathis

Abstract. In this paper, we present a method to increase the time resolution of a pulse width modulator by using delay lines. The modulator is part of an open loop class D power amplifier, which uses the ZePoC algorithm to code the audio signal which is amplified in the class D power stage. If the time resolution of the pulse width modulator is high enough, ZePoC could also be used to build an high accuracy AC power standard, because of its open loop property. With the presented method the time resolution theoretically could be increased by a factor of 16, which means here the time resolution will be enhanced from 5 ns to 312.5 ps.


Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 100
Author(s):  
Miguel Fernandez ◽  
Alberto Rodriguez ◽  
Miguel Rodríguez ◽  
Aitor Vazquez ◽  
Pablo Fernandez ◽  
...  

This paper proposes a simple, hardware-efficient digital pulse width modulator for a 4SBB that enables operation in Buck, Boost, and Buck+Boost modes, achieving smooth transitions between the different modes. The proposed modulator is simulated using Simulink and experimentally demonstrated using a 500 W 4SBB converter with 24 V input voltage and 12–36 V output voltage range.


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