scholarly journals Increasing the time resolution of a pulse width modulator in a class D power amplifier by using delay lines

2014 ◽  
Vol 12 ◽  
pp. 91-94 ◽  
Author(s):  
M. Weber ◽  
T. Vennemann ◽  
W. Mathis
Keyword(s):  
Power Amplifier ◽  
Time Resolution ◽  
Pulse Width ◽  
Audio Signal ◽  
Open Loop ◽  
Delay Lines ◽  
Class D ◽  
Ac Power ◽  
Pulse Width Modulator ◽  
Power Stage

Abstract. In this paper, we present a method to increase the time resolution of a pulse width modulator by using delay lines. The modulator is part of an open loop class D power amplifier, which uses the ZePoC algorithm to code the audio signal which is amplified in the class D power stage. If the time resolution of the pulse width modulator is high enough, ZePoC could also be used to build an high accuracy AC power standard, because of its open loop property. With the presented method the time resolution theoretically could be increased by a factor of 16, which means here the time resolution will be enhanced from 5 ns to 312.5 ps.

A Mixed-Signal RF Pulse Width Modulator With High Time Resolution Utilizing Passive Delay Lines

2020 ◽  
Vol 67 (11) ◽  
pp. 2442-2446
Author(s):  
Yannis Papananos ◽  
Kostas Galanopoulos ◽  
Nikolaos Alexiou ◽  
Franz Dielacher
Keyword(s):  
Time Resolution ◽  
Pulse Width ◽  
High Time ◽  
High Time Resolution ◽  
Delay Lines ◽  
Mixed Signal ◽  
Pulse Width Modulator ◽  
Rf Pulse

scholarly journals Class D Power Amplifier Used In Programmable Ac Power Source Ideal To Analyse Electronic Equipment Performance In The Electrical Power System Quality

2009 ◽  
Vol 14 (1) ◽  
pp. 9-16
Author(s):  
Fábio Vincenzi Romualdo da Silva ◽  
João Batista Vieira Júnior ◽  
Ernane Antônio Alves Coelho ◽  
Valdeir José Farias ◽  
Luiz Carlos de Freitas
Keyword(s):  
Power System ◽  
Power Amplifier ◽  
Electrical Power ◽  
Power Source ◽  
Electronic Equipment ◽  
System Quality ◽  
Electrical Power System ◽  
Class D ◽  
Ac Power ◽  
Equipment Performance

scholarly journals Improved Error Correction Methods for Filterless Digital Class D Audio Power Amplifier Based on FCLNF

2020 ◽  
Vol 2020 ◽  
pp. 1-9
Author(s):  
Li Li ◽  
Hong-jie Li ◽  
Yan-jing Sun
Keyword(s):  
Error Correction ◽  
Power Amplifier ◽  
Power Supply ◽  
Cmos Process ◽  
Power Supply Noise ◽  
First Order ◽  
Supply Noise ◽  
Class D ◽  
Power Stage ◽  
The Impact

Aiming at correcting the error caused by the nonlinear and power supply noise of the bridge-tied-load (BTL) power stage of the filterless digital class D power amplifier, an error correction method was proposed based on feedforward power supply noise suppression (FFPSNS) and first-order closed loop negative feedback (FCLNF) techniques. This method constructed the first-order LCLNF loop for the power stage and further reduced the impact of the power supply noise on the power amplifier output by using FFPSNS technology to introduce the power supply noise into the feedback loop at the same time. The 0.35 μm CMOS process is used for analysis and comparison in Cadence. Cadence simulation results indicate that PSRR at the power supply noise frequency of 200 Hz is improved with 36.02 dB. The power supply induced intermodulation distortion (PS-IMD) components are decreased by approximately 15.57 dB and the signal-to-noise ratio (SNR) of the power amplifier is increased by 17 dB. The total harmonic distortion + noise (THD + N) of the power amplifier is reduced to 0.02% by FCLNF + FFPSNS.

Design and test of a pulse-width modulator and driver for space-borne GaN switch mode power amplifiers in P-band

2015 ◽  
Vol 7 (3-4) ◽  
pp. 297-305 ◽  
Author(s):  
I. S. Ghosh ◽  
U. Altmann ◽  
L. Cabria ◽  
E. Cipriani ◽  
P. Colantonio ◽  
...  
Keyword(s):  
High Power ◽  
Pulse Width ◽  
Three Dimensional ◽  
Buffer Size ◽  
Single Chip ◽  
Test Chip ◽  
Simulation Accuracy ◽  
Electromagnetic Simulations ◽  
Pulse Width Modulator ◽  
Power Stage

In this paper, the design and test of a single-chip RF pulse-width modulator and driver (PWMD) aimed at exciting a high-power class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller test chip capable of driving capacitive loads of up to 5 pF was initially designed, fabricated, and tested. An approach based on three-dimensional electromagnetic simulations was used to validate the test results and offers excellent simulation accuracy. Based on the results obtained for test chip an enlarged PWMD chip capable of driving a 40 W high-power stage has been designed and tested on passive loads representing the targeted final stage.

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