A 405-MHz 850-μW Low-Noise Amplifier with 53.5-dB Voltage Gain and 100-ns Settling Time

Author(s):  
Rui Ma ◽  
Naglaa El Agroudy ◽  
Niko Joram ◽  
Frank Ellinger
Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1966
Author(s):  
Yiming Han ◽  
Fengjie Wang ◽  
Jiarui Liu ◽  
Zhiyu Wang ◽  
Faxin Yu

To improve the linearity of direct conversion receivers (DCRs), two high-linearity methods for high second-order intercept points (IP2s) and high third-order intercept points (IP3s) are proposed. To improve IP3s, a transconductance equalization technique for a complementary input operational amplifier (OPAMP) is proposed in an active-RC low-pass filter (LPF), while a digital-analog hybrid DC offset calibration (DCOC) method is proposed to improve IP2s. For one thing, the proposed transconductance equalization technique employs a pair of resistors to guarantee high voltage gain for an OPAMP with two-stage Miller topology under a high-input voltage swing to improve linearity with little deterioration of the noise performance. For another, during the DCOC method, the low-noise amplifier is turned off and replaced by an equivalent resistance of the output impedance of the low-noise amplifier to ensure the accuracy and effectiveness of the DCOC method. Fabricated in 40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of −53.2 dBm under the total voltage gain of 60 dB.


2018 ◽  
Vol 32 (02) ◽  
pp. 1850009 ◽  
Author(s):  
Benqing Guo ◽  
Jun Chen ◽  
Hongpeng Chen ◽  
Xuebing Wang

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.


2018 ◽  
Vol E101.C (1) ◽  
pp. 82-90
Author(s):  
Chang LIU ◽  
Zhi ZHANG ◽  
Zhiping WANG

Author(s):  
Z. Zhang ◽  
Z.H. Li ◽  
W.R. Zhang ◽  
F.Y. Zhao ◽  
C.L. Chen ◽  
...  

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