A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

2018 ◽  
Vol 32 (02) ◽  
pp. 1850009 ◽  
Author(s):  
Benqing Guo ◽  
Jun Chen ◽  
Hongpeng Chen ◽  
Xuebing Wang
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Voltage Gain ◽  
Third Order ◽  
Weak Inversion ◽  
Linearization Technique ◽  
The Third ◽  
Noise Amplifier ◽  
Second Order Nonlinearity

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

2009 ◽  
Vol 30 (1) ◽  
pp. 015001 ◽  
Author(s):  
Yang Yi ◽  
Gao Zhuo ◽  
Yang Liqiong ◽  
Huang Lingyi ◽  
Hu Weiwu
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Noise Amplifier

Optimization of Linearity in CMOS Low Noise Amplifier

2012 ◽  
pp. 1-14
Author(s):  
Thierry Taris ◽  
Aya Mabrouki
Keyword(s):  
Power Consumption ◽  
Drain Current ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
The Third ◽  
Operating Region ◽  
Promising Solution ◽  
Noise Amplifier

In this chapter the authors evaluate a new and promising solution to the problem of power consumption based on “optimum gate biasing.” This technique consists in tracking the MOS operating region wherein the third derivation of drain current is zero. The method leads to a significant IIP3 improvement; however, the sensitivity to process drifts requires the use of a specific bias circuit to track the optimum biasing condition.

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