Quantifying the error contribution of noise parameters on Y-factor noise figure measurements

Author(s):  
Ken Wong ◽  
Ken Wong ◽  
Joe Gorin ◽  
Guoquan Lu
Author(s):  
Asmaa Nur Aqilah Zainal Badri ◽  
Norlaili Mohd Noh ◽  
Shukri Bin Korakkottil Kunhi Mohd ◽  
Asrulnizam Abd Manaf ◽  
Arjuna Marzuki ◽  
...  

Accurate transistor thermal noise model is crucial in IC design as it allows accurate selection of transistors for specific frequency application. The accuracy of the model is represented by the similarity between the simulated and the measured noise parameters (NPs). This work was based on a problem faced by a foundry concerning the dissimilarities between the measured and simulated NPs, especially minimum noise figure (NF<sub>min</sub>) for frequencies below 3 GHz.


2005 ◽  
Vol 05 (03) ◽  
pp. L423-L433 ◽  
Author(s):  
A. CADDEMI ◽  
F. CATALFAMO ◽  
N. DONATO

In this paper we report the development of an artificial neural network to extract a 17-element small-signal circuit model of high electron mobility transistors (HEMTs) and one associated noise temperature value. By this procedure, we are able to reproduce the small-signal and noise performance of several device types from only one measured scattering parameter set, one frequency point and one noise figure value. The employed noise figure is measured in input matched conditions (i.e. 50 Ω source impedance), namely F 50. The output noise temperature is associated to the drain-source resistance in the HEMT equivalent circuit according to the noise temperature model by Pospieszalski. The noise parameters of the device under test are then calculated by CAD simulation of the circuit and compared with measurement results. The trained network outputs were used by means of a commercial CAD tool, to simulate and fit measurements performed down to cryogenic temperatures with very good agreement. We observed that the difference that occurs between the expected value of the noise temperature and the average value calculated by the neural network leads to negligible variations in the behavior of the simulated noise parameters.


1998 ◽  
Vol 34 (3) ◽  
pp. 289 ◽  
Author(s):  
A. Lázaro ◽  
L. Pradell ◽  
A. Beltrán ◽  
J.M. O'Callaghan

1996 ◽  
Vol 74 (S1) ◽  
pp. 195-199 ◽  
Author(s):  
M. Jamal Deen

This paper presents detailed results from modelling the four noise parameters: minimum noise figure (NFMIN), noise resistance (RN), optimal source resistance (RS,OPT), and reactance (XS,OPT) as functions of frequency and collector-biasing current. Compared to previous BJT (bipolar junction transistor) high-frequency noise models, we include the emitter resistance, which results in an increased input device impedance, and a degeneration of the device transconductance. We also give an explicit formula for the noise resistance. We present noise results for polysilicon emitter bipolar transistors as a function of emitter areas to demonstrate how the noise parameters scale with emitter areas over a range of frequencies. However, these results are given only for devices in which the pad impedances are much larger than the device input impedance, so that very little input signal is lost through the pads to ground.


Author(s):  
Asmaa Nur Aqilah Zainal Badri ◽  
Norlaili Mohd Noh ◽  
Shukri Bin Korakkottil Kunhi Mohd ◽  
Asrulnizam Abd Manaf ◽  
Arjuna Marzuki ◽  
...  

<p>This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi- finger layouts. The doughnut style involves the polygonal and the 4- sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut, and the narrow-OD with multi-fingers versus multi-OD with multi- fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cut- off frequency (f<sub>T</sub>) and the maximum frequency (f<sub>MAX</sub>), whereas the noise parameters involved are noise resistance (R<sub>N</sub>) and the minimum noise figure (NF<sub>min</sub>). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (G<sub>m</sub>); gate resistance (R<sub>g</sub>); effective mobility (μ<sub>eff</sub>); and parasitic capacitances (c<sub>gg</sub> and c<sub>gd</sub>). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4- sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in f<sub>T</sub> and f<sub>MAX</sub>, owing partly to the improvement in G<sub>m</sub>, μ<sub>eff</sub>, c<sub>gg</sub>, c<sub>gd</sub> and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in f<sub>T</sub> due to a lower G<sub>m</sub>. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for f<sub>T</sub>, f<sub>MAX</sub>, G<sub>m</sub> and μ<sub>eff</sub> but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of c<sub>gg</sub> as the transistor becomes narrower, whereas a multi-OD multi-finger may have high R<sub>g</sub> and therefore may lead to the increase of f<sub>T</sub> and f<sub>MAX</sub> as the transistor becomes narrower. Besides, the doughnut layout style has a higher G<sub>m</sub> and f<sub>T</sub>, leading to larger μ<sub>eff</sub> from the elimination of shallow trench isolation (STI) stress.</p>


2016 ◽  
Vol 9 (4) ◽  
pp. 821-829 ◽  
Author(s):  
Abdul-Rahman Ahmed ◽  
Dong-Hyun Lee ◽  
Kyung-Whan Yeom

In this paper, we demonstrate the successful implementation of an onwafer noise parameters test set that employs an extended six-port network and a conventional noise figure analyzer. The necessary formulation that enables the calibration of the noise parameter test set as well as extraction of the noise wave correlation matrix of a two-port device under test (DUT) was tested for coaxial connector-type DUT measurement in an earlier work but not for onwafer-type DUT. Furthermore, we demonstrate the performance of this technique against data obtained from the well-known tuner method. Measurement carried out for very low-noise figure (2 dB) onwafer-type amplifier demonstrates the capability of our technique. The measured noise parameters show fluctuations in minimum noise figure, NFminof ±0.1 dB, and in noise resistance Rnof about 2%. This test set is simple and fast leading to tremendous time- and cost-savings as well as a simplified procedure in onwafer noise parameters measurements.


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