System-on-a-chip global interconnect optimization

15th Annual IEEE International ASIC/SOC Conference ◽

10.1109/asic.2002.1158092 ◽

2003 ◽

Author(s):

A. Naeemi ◽

R. Venkatesan ◽

J.D. Meindl

Keyword(s):

Interconnect Optimization ◽

System On A Chip ◽

Global Interconnect

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A global interconnect design window for a three-dimensional system-on-a-chip

10.1109/iitc.2001.930044 ◽

2001 ◽

Author(s):

J.W. Joyner ◽

P. Zarkesh-Ha ◽

J.D. Meindl

Keyword(s):

Three Dimensional ◽

Dimensional System ◽

System On A Chip ◽

Global Interconnect ◽

Interconnect Design ◽

Three Dimensional System

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The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip

2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) ◽

10.1109/eiconrus49466.2020.9039182 ◽

2020 ◽

Author(s):

Mariya A. Zapletina ◽

Daniil A. Zheleznikov ◽

Sergey V. Gavrilov

Keyword(s):

Reconfigurable System ◽

System On A Chip ◽

Global Interconnect ◽

Interconnect Routing

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A Global Interconnect Optimization Scheme for Nanometer Scale VLSI With Implications for Latency, Bandwidth, and Power Dissipation

IEEE Transactions on Electron Devices ◽

10.1109/ted.2003.820651 ◽

2004 ◽

Vol 51 (2) ◽

pp. 195-203 ◽

Author(s):

M.L. Mui ◽

K. Banerjee ◽

A. Mehrotra

Keyword(s):

Power Dissipation ◽

Nanometer Scale ◽

Optimization Scheme ◽

Interconnect Optimization ◽

Global Interconnect

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Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

Microelectronics Journal ◽

10.1016/j.mejo.2004.06.017 ◽

2004 ◽

Vol 35 (10) ◽

pp. 849-857 ◽

Author(s):

Mariagrazia Graziano ◽

Mario R. Casu ◽

Guido Masera ◽

Gianluca Piccinini ◽

Maurizio Zamboni

Keyword(s):

Deep Submicron ◽

Future Technology ◽

Interconnect Optimization ◽

Effects Of Temperature ◽

Global Interconnect ◽

Technology Nodes

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Global interconnect design in a three-dimensional system-on-a-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2004.825835 ◽

2004 ◽

Vol 12 (4) ◽

pp. 367-372 ◽

Author(s):

J.W. Joyner ◽

P. Zarkesh-Ha ◽

J.D. Meindl

Keyword(s):

Three Dimensional ◽

Dimensional System ◽

System On A Chip ◽

Global Interconnect ◽

Interconnect Design ◽

Three Dimensional System

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Global interconnect optimization with simultaneous macrocell placement and repeater insertion

IEEE International SOC Conference, 2004. Proceedings. ◽

10.1109/socc.2004.1362456 ◽

2004 ◽

Author(s):

Yuantao Peng ◽

Xun Liu

Keyword(s):

Interconnect Optimization ◽

Global Interconnect

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Global Interconnect Optimization in the Presence of On-chip Inductance

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378048 ◽

2007 ◽

Author(s):

Abinash Roy ◽

Masud H. Chowdhury

Keyword(s):

Interconnect Optimization ◽

Global Interconnect ◽

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Effects of Temperature in Deep-Submicron Global Interconnect Optimization

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-39762-5_11 ◽

2003 ◽

pp. 90-100 ◽

Author(s):

M. R. Casu ◽

M. Graziano ◽

G. Piccinini ◽

G. Masera ◽

M. Zamboni

Keyword(s):

Deep Submicron ◽

Interconnect Optimization ◽

Effects Of Temperature ◽

Global Interconnect

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Global Interconnect Optimization

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad45719.2019.8942155 ◽

2019 ◽

Author(s):

Siad Daboul ◽

Stephan Held ◽

Bento Natura ◽

Daniel Rotter

Keyword(s):

Interconnect Optimization ◽

Global Interconnect

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A Global Interconnect Optimization Algorithm under Accurate Delay Model Using Solution Space Smoothing

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1464532 ◽

2005 ◽

Author(s):

Yici Cai ◽

Yibo Wang ◽

Xianlong Hong

Keyword(s):

Optimization Algorithm ◽

Solution Space ◽

Delay Model ◽

Interconnect Optimization ◽

Global Interconnect ◽

Accurate Delay Model

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