scholarly journals Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

2004 ◽  
Vol 35 (10) ◽  
pp. 849-857 ◽  
Author(s):  
Mariagrazia Graziano ◽  
Mario R. Casu ◽  
Guido Masera ◽  
Gianluca Piccinini ◽  
Maurizio Zamboni
2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Nisha Kuruvilla ◽  
J. P. Raina

CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.


2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.


2012 ◽  
Vol 11 (1) ◽  
pp. 56-62 ◽  
Author(s):  
Jonathan W. Ward ◽  
Jonathan Nichols ◽  
Timothy B. Stachowiak ◽  
Quoc Ngo ◽  
E. James Egerton

2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.


2006 ◽  
Author(s):  
Madhavi Chandrachood ◽  
Michael Grimbergen ◽  
Toi Yue B. Leung ◽  
Keven Yu ◽  
Renee Koch ◽  
...  

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 53196-53202 ◽  
Author(s):  
Daniel Nagy ◽  
Gabriel Espineira ◽  
Guillermo Indalecio ◽  
Antonio J. Garcia-Loureiro ◽  
Karol Kalna ◽  
...  

Author(s):  
Fahimul Islam Sakib ◽  
Md. Azizul Hasan ◽  
Mainul Hossain

Abstract Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.


2019 ◽  
Vol 66 (8) ◽  
pp. 3608-3613
Author(s):  
Tarun Kumar Agarwal ◽  
Martin Rau ◽  
Iuliana Radu ◽  
Mathieu Luisier ◽  
Wim Dehaene ◽  
...  

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