scholarly journals A Global Interconnect Optimization Scheme for Nanometer Scale VLSI With Implications for Latency, Bandwidth, and Power Dissipation

2004 ◽  
Vol 51 (2) ◽  
pp. 195-203 ◽  
Author(s):  
M.L. Mui ◽  
K. Banerjee ◽  
A. Mehrotra
Author(s):  
Udo D. Schwarz ◽  
Claudia Ritter ◽  
Markus Heyde ◽  
Klaus Rademann

Antimony nanoparticles grown on highly oriented pyrolytic graphite and molybdenum disulfide were used as a model system to investigate the contact area dependence of frictional forces. Controlled translation of the antimony nanoparticles was induced by the action of the oscillating tip in a dynamic force microscope. During manipulation, the power dissipated due to tip-sample interactions was recorded. We found that the threshold value of the power dissipation needed for translation depends linearly on the contact area between the antimony particles and the substrate. Assuming a linear relationship between dissipated power and frictional forces implies a direct proportionality between friction and contact area. Particles smaller than 10000 nm2, however, were found to show dissipation close to zero. To explain the observed behavior, we suggest that structural lubricity might be the reason for the low dissipation in the small particles, while elastic multistabilities might dominate energy dissipation in the larger particles.


2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.


2005 ◽  
Vol 52 (10) ◽  
pp. 2272-2279 ◽  
Author(s):  
X.-C. Li ◽  
J.-F. Mao ◽  
H.-F. Huang ◽  
Y. Liu

2004 ◽  
Vol 35 (10) ◽  
pp. 849-857 ◽  
Author(s):  
Mariagrazia Graziano ◽  
Mario R. Casu ◽  
Guido Masera ◽  
Gianluca Piccinini ◽  
Maurizio Zamboni

2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Xin Niu

In the lossy wireless network routing system based on RPL technology, an improved DODAG construction optimization scheme is proposed for sensor nodes with low-power dissipation in the interference environment. If a node discovers that all paths between it and its neighbors have failed, the node reset action begins. Once the node reset is complete, the DODAG system build process is resumed. This prevents the DODAG root from initiating a global fix by incrementing the DODAG VersionNumer to produce a new version of the DODAG in a disruptive environment. The power loss caused by this global repair operation is avoided. The performance of DODAG in interference environment is enhanced, and the data retransmission rate is reduced.


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