Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. Si NS MOSFETs provide high current drivability due to wider effective channel (Weff) and maintain better short channel performance. Here, the performance of junctionless (JL) NS p-MOSFET was evaluated by invoking HfxTi1-xO2 gate stack. The device performance was enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on ION/IOFF, SS, Vth is presented and the analog/RF metrics of the device are evaluated. The power analysis of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an ION/IOFF ratio of more than ~106 with NS widths of 10 to 30 nm, respectively. For high-performance applications, the device exhibits better performance (ION) with higher NS widths. However, the threshold voltage downfall leads to deterioration in subthreshold performance with an increase in NS widths. With Si3N4 as a spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes

The temperature-dependent modeling technique (in the temperature range of 200–500[Formula: see text]K) for a mixed class of carbon nanotube (CNT) bundle interconnects is proposed. The equivalent single conductor (ESC) transmission line models of multi-walled carbon nanotube (MWCNT) and double-walled carbon nanotube (DWCNT) are combined to develop multiple single conductor (MSC) model of mixed CNT interconnects. Various possible arrangements of densely packed MWCNT and DWCNT bundles (MDCB) are considered to form different types of mixed CNT bundle structures (MDCB-1, MDCB-2, MDCB-3 and MDCB-4). The integrated circuit emphasis simulation is performed and the performances of these mixed CNT bundle interconnects are investigated in terms of propagation delay (with and without crosstalk), power dissipation, power-delay product (PDP). Switching times, overshoot voltages and Nyquist plots are analyzed to check the stability of these mixed CNT structures for global interconnect length for 32-nm, 22-nm and 16-nm technology nodes. It is observed that the MDCB-1 structure yields the most promising result in all aspects for interconnect applications in the near future.

Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method

High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.