In this paper a top-down methodology is presented for synthesizing clock distribution
networks based on application-dependent localized clock skew. The methodology is
divided into four phases: 1) determination of an optimal clock skew schedule for
improving circuit performance and reliability; 2) design of the topology of the clock tree
based on the circuit hierarchy and minimum clock path delays; 3) design of circuit
structures to implement the delay values associated with the branches of the clock tree;
and 4) design of the geometric layout of the clock distribution network. Algorithms to
determine an optimal clock skew schedule, the optimal clock delay to each register, the
network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS
technology and a design strategy based on this technology is presented to implement the
individual branch delays. The minimum number of inverters required to implement the
branch delays is determined, while preserving the polarity of the clock signal. The clock
lines are transformed from distributed resistive-capacitive interconnect lines into purely
capacitive interconnect lines by partitioning the RC interconnect lines with inverting
repeaters. The inverters are specified by the geometric size of the transistors, the slope of
the ramp shaped input/output waveform, and the output load capacitance. The branch
delay model integrates an inverter delay model with an interconnect delay model.
Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock
skew between any two registers belonging to the same global data path are obtained as
compared with SPICE Level-3.