A non-zero clock skew scheduling algorithm for high speed clock distribution network

2003 ◽  
Author(s):  
M.B. Maaz ◽  
M.A. Bayoumi
Keyword(s):  
High Speed ◽  
Scheduling Algorithm ◽  
Distribution Network ◽  
Clock Distribution ◽  
Clock Skew ◽  
Clock Distribution Network ◽  
Clock Skew Scheduling

Clock Skew Analysis in Optical Clock Distribution Network

2007 ◽  
Author(s):  
Grzegorz Tosik ◽  
Filip Abramowicz ◽  
Zbigniew Lisik ◽  
Frederic Gaffiot
Keyword(s):  
Distribution Network ◽  
Optical Clock ◽  
Clock Distribution ◽  
Clock Skew ◽  
Clock Distribution Network

scholarly journals DEMONSTRATION OF SPEED AND POWER ENHANCEMENTS ON AN INDUSTRIAL CIRCUIT THROUGH APPLICATION OF CLOCK SKEW SCHEDULING

2002 ◽  
Vol 11 (03) ◽  
pp. 231-245 ◽  
Author(s):  
D. VELENIS ◽  
K. T. TANG ◽  
I. S. KOURTEV ◽  
V. ADLER ◽  
F. BAEZ ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Scheduling Algorithm ◽  
Software Tool ◽  
Clock Signal ◽  
Clock Skew ◽  
Circuit Performance ◽  
Power Characteristics ◽  
Critical Data ◽  
Clock Skew Scheduling

A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated in this paper. It is shown that nonzero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a nonzero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays. Furthermore, a technique that significantly reduces the power dissipated in the noncritical data paths is demonstrated. The application of this technique combined with nonzero clock skew scheduling to the slower data paths is also described. Speed improvements of up to 18% and power savings greater than 80% are achieved in certain functional blocks of an industrial high performance microprocessor.

A HIGH FLEXIBILITY DESIGN FOR CLOCK DISTRIBUTION NETWORK IN SYSTEM ON CHIP

2007 ◽  
Vol 16 (01) ◽  
pp. 51-63
Author(s):  
CHI-CHOU KAO
Keyword(s):  
High Speed ◽  
Distribution Network ◽  
Clock Signal ◽  
Clock Distribution ◽  
Single Chip ◽  
New Approach ◽  
Flexibility Design ◽  
Clock Distribution Network ◽  
On Chip ◽  
High Flexibility

The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.

scholarly journals Automated Synthesis of Skew-Based Clock Distribution Networks

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 31-57 ◽  
Author(s):  
José Luis Neves ◽  
Eby G. Friedman
Keyword(s):  
Distribution Network ◽  
Distribution Networks ◽  
Clock Signal ◽  
Clock Distribution ◽  
Delay Model ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Distribution Networks ◽  
Clock Distribution Network ◽  
Interconnect Lines

In this paper a top-down methodology is presented for synthesizing clock distribution networks based on application-dependent localized clock skew. The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance and reliability; 2) design of the topology of the clock tree based on the circuit hierarchy and minimum clock path delays; 3) design of circuit structures to implement the delay values associated with the branches of the clock tree; and 4) design of the geometric layout of the clock distribution network. Algorithms to determine an optimal clock skew schedule, the optimal clock delay to each register, the network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS technology and a design strategy based on this technology is presented to implement the individual branch delays. The minimum number of inverters required to implement the branch delays is determined, while preserving the polarity of the clock signal. The clock lines are transformed from distributed resistive-capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. The inverters are specified by the geometric size of the transistors, the slope of the ramp shaped input/output waveform, and the output load capacitance. The branch delay model integrates an inverter delay model with an interconnect delay model. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock skew between any two registers belonging to the same global data path are obtained as compared with SPICE Level-3.

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