РАСЧЕТ СОПРОТИВЛЕНИЯ ЭЛЕМЕНТОВ МЕТАЛЛИЗАЦИИ ГЛУБОКО СУБМИКРОННЫХ СБИС

Проводится расчет элементов системы металлизации, который может быть применим для оценки сопротивления контактных окон, переходных окон, линий металлизации различных геометрий и топологических норм, а также для предварительного диагностирования дефектных пустот, образующихся в контактных и переходных окнах. The paper presents interconnect elements resistance calculation that can be used to assess the resistance of contact plugs, vias, interconnect lines of various geometries and technology nodes, as well as for the preliminary diagnosis of defective voids formed in the contact plugs and vias.

Novel Approach to Analyze Crosstalk for a Multi-Line Bus System at 32-nm Technology

This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100[Formula: see text][Formula: see text]m and 1,000[Formula: see text][Formula: see text]m interconnect lengths, respectively.

Effect of Lines and Vias Density on the BEOL Temperature Distribution

A method to calculate the temperature distribution on the BEOL structure and its impact on the EM in a design environment has been developed and implemented. The study for a 45 nm technology indicated a large temperature variation from the local to the global interconnects, which should be considered for the EM induced resistance increase of the line, in contrast to the standard analysis through a fixed operation temperature throughout the BEOL. The results show that a significant additional temperature above 50°C exist on the layers M1 to M6 due the power dissipated from transistors. The temperature reduction on the local layer is evaluated increasing the number of vias and enlarging the interconnect lines, both with a direct influence on the BEOL thermal distribution. A reduction of 62.9°C is obtained for M1 layer, considering a fraction volume of 40% for lines and 6% for vias.

Scanning microwave microscopy of buried CMOS interconnect lines with nanometer resolution

This paper reports scanning microwave microscopy of CMOS interconnect aluminum lines both bare and buried under oxide. In both cases, a spatial resolution of 190 ± 70 nm was achieved, which was comparable or better than what had been reported in the literature. With the lines immersed in water to simulate high-k dielectric, the signal-to-noise ratio degraded significantly, but the image remained as sharp as before, especially after averaging across a few adjacent scans. These results imply that scanning microwave microscopy can be a promising technique for non-destructive nano-characterization of both CMOS interconnects buried under oxide and live biological samples immersed in water.