A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique

2016 ◽  
Author(s):  
Tsung-Chih Hung ◽  
Tai-Haur Kuo
Keyword(s):  
Pipelined Adc ◽  
Correlated Level Shifting

VLSI DESIGN OF PIPELINED ADC WITH WIDE RANGE OPERATING TEMPERATURE FOR WAVE APPLICATIONS

2017 ◽  
Vol 6 (2) ◽  
pp. 13
Author(s):  
P LOKESH ◽  
U. SOMALATHA ◽  
S. CHANDANA ◽  
◽  
◽  
...  
Keyword(s):  
Operating Temperature ◽  
Vlsi Design ◽  
Pipelined Adc ◽  
Wide Range

scholarly journals Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

2020 ◽  
Vol 981 ◽  
pp. 032046
Author(s):  
Y. Srikanth ◽  
Ch. Rajendra Prasad ◽  
Koteshwar Rao Danthamala ◽  
P. Ramchandar Rao ◽  
A. Chakradhar
Keyword(s):  
Error Correction ◽  
Pipelined Adc
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