This paper presents a voltage level shifter (VLS) based on two feedback loops. The complementary feedback signals in the high voltage domain are re-used to assist voltage conversion and the complementary phase in the low voltage domain is not required. Unlike the conventional VLS, which depends on the pull-up network and pull-down network to achieve level shift, the transitions of both high-to-low and low-to-high of the proposed VLS are undertaken by two different feedback loops, respectively. Implemented in a standard 180 nm CMOS process, post-layout Monte Carlo (MC) simulations from 4000 points under mismatch variation show that the dynamic power (DP) and the propagation delay (PD) of the proposed VLS are 105.3 nW and 2.0 ns, respectively, at an input voltage VIN = 0.4 V with input frequency fin = 0.1 MHz. Meanwhile, the excellent normalized standard deviation of DP and PD is obtained with the proposed scheme. The temperature range for normal operation is from −20 °C to 85 °C.
An Area and Energy Efficient Ultra-Low Voltage Level Shifter With Pass Transistor and Reduced-Swing Output Buffer in 65-nm CMOS