FPGA implementation of floating-point complex matrix inversion based on GAUSS-JORDAN elimination

2013 ◽  
Author(s):  
Sherif Moussa ◽  
Ahmed M. Abdel Razik ◽  
Adel Omar Dahmane ◽  
Habib Hamam
Keyword(s):  
Matrix Inversion ◽  
Fpga Implementation ◽  
Floating Point ◽  
Complex Matrix

scholarly journals Floating Point versus Fixed point Tradeoffs in FPGA Implementations of QR Decomposition Algorithm

2019 ◽  
Vol 3 (5) ◽  
Author(s):  
Siavash Amin-Nejad ◽  
Katayoon Basharkhah ◽  
Tayyebeh Asgari Gashteroodkhani
Keyword(s):  
Communication Systems ◽  
Qr Decomposition ◽  
Matrix Inversion ◽  
Floating Point ◽  
Clock Frequency ◽  
Complex Matrix ◽  
Vector Processing ◽  
Point Versus ◽  
Digital Communication Systems ◽  
Processing Architecture

A wide variety of digital communication systems are encountered with high computational tasks. QR decomposition is one of such algorithms that can be implemented on FPGAs as a solution to large complex matrix inversion problems. A flexible vector processing architecture for the fixed and floating point implementations of the QR decomposition is presented. The design is implemented on the StratixIV device with 230K logic elements and verified with the SignalTap II built-in logic analyzer. Throughputs of 2.4M and 2.11M decompositions per second with maximum clock frequency of 340 MHz and 360 MHz are achieved for 4×4 matrices with the fixed and floating point designs respectively. The FPGA resource utilizations of the two data type implementations are also compared for different matrix sizes for the StratixIV and Arria10 devices.

The FPGA Implementation of Single-Precision Floating-Point Adder

2014 ◽  
Vol 1008-1009 ◽  
pp. 668-671
Author(s):  
Hai Ke Liu ◽  
Xin Gna Kang ◽  
Shun Wang
Keyword(s):  
Real Number ◽  
Fpga Implementation ◽  
Floating Point ◽  
Single Precision ◽  
Operation Process ◽  
Storage Format ◽  
Process Ability

A design of single precision floating point adder based on FPGA is presented,by analysing the form of real number formed on IEEE 754 and the storage format of IEEE 754 single-precision floating point,the addition arithmetic process which is easy to realized by using FPGA is put forward,the split of module based on the arithmetic process facilitates the realization of pipeline designing,so the single precision floating point adder introduce by this paper has powerful operation process ability.

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