The quantum incrementer is one of the simplest quantum operators, which exhibits basic arithmetic operations such as addition, the propagation of carry qubits and the resetting of carry qubits. In this paper, three quantum incrementer gate circuit topologies are derived and compared based upon their total number of gates, the complexity of the circuits, the types of gates used and the number of carry or ancilla qubits implemented. The first case is a generalized n-qubit quantum incrementer gate with the notation of (n:0). Two other quantum incrementer topologies are proposed with the notations of (n:n-1: RE ) and (n:n-1: RD ). A general method is derived to decompose complicated quantum circuits into simpler quantum circuits which are easier to manage and physically implement. Due to the cancelation of intermediate unitary gates, it is shown that adding ancilla qubits slightly increases the complexity of a given circuit by the order of 3n, which pales in comparison to the complexity of the original circuit of the order n2 without reduction. Finally, a simple application of the generalized n-qubit quantum incrementer gate is introduced, which is related to quantum walks.
Reversible Logic Circuit Synthesis and Optimization Using Adaptive Genetic Algorithm
