FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

Smart Car Parking System

Nowadays, the internet of things plays a crucial role in our life by connecting things with humans via the web. This study proposes a sensible system supported Arduino components, website and mobile application. The system helps drivers to seek out an empty park space counting on the amount of unoccupied lots within the park. The parking lots are impossible to be reserved with the standard parking system. This study provides a mobile app which will be utilised to seek out a free lot during a nearest park. Smart parking also help to reduce the pollution in cities as it help in fuel consumption. Moreover, it helps to scale back the time of finding car lot. Also, it helps the person who is driving to seek out his car when he forgets the car location easily. However; the system adopts new tables’ structure, yellow booking light within the parking zone, books and buys through app & gate circuit monitor. Finally, the system shows the reserved, booked and empty lots in park for workers and drivers.

Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder

Fast adders are constructed mainly by Carry select adders (CSLA). Area is one of the main concerns as far as any VLSI design is considered. In connection this paper enhances the performance of self checking carry select adder by introducing un footed dynamic logic based full adder cell instead of a regular CMOS based adders. The adder is constructed with 10 transistors based on the optimization of truth tale of a full adder. A 3 transistor X-NOR gate circuit is also used instead of a conventional X-NOR circuit in the self checking path. Adders of size 4 bit and 8 bit are constructed in various technologies. The results show that the proposed structure reduces the transistor over head by almost 47% and 46% for 4bit and 8bit structures respectively. By achieving this much of reduction in area this work could be suggested for higher order VLSI structures like BIST,DCT etc.,

Construction of Nanobody Library in Mammalian Cells by Linear-double-stranded DNA Based AND Gate Genetic Circuit

Nanobody is one special type of single-domain antibody fragment with multiple advantages over traditional antibody. Our previous work established linear-double-stranded DNA (ldsDNA, or PCR amplicon) as novel biological parts for building AND gate genetic circuits in mammalian cells. During this AND-gate circuit formation process, the co-transfected up- and down-stream ldsDNAs could be linked together to form intact gene expression cassette. Here, we employed this ldsDNA-based AND-gate (LBAG) strategy to construct nanobody library in mammalian cells. The sequence complexity of complementary determining regions (CDRs) was introduced into ldsDNA by PCR amplification. After being co-transfected into mammalian cells, the up- and down- stream ldsDNAs undergo AND gate linkage and form full nanobody coding regions, containing CDR1-3. High throughput sequencing identified 22,173 unique oligonucleotide sequences in total generated by this strategy. Thus, we developed a novel method to construct nanobody library, which is a start point for building high content nanobody library in mammalian cells.