A 3 mW 1.2–3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth

2018 ◽  
Vol 27 (08) ◽  
pp. 1850117 ◽  
Author(s):  
Jili Zhang ◽  
Yu Li ◽  
Shengxi Diao ◽  
Xuefei Bai ◽  
Fujiang Lin
Keyword(s):  
Low Frequency ◽  
Cmos Process ◽  
Clock Generator ◽  
Loop Filter ◽  
Time Period ◽  
Loop Bandwidth ◽  
Reference Spur ◽  
On Chip ◽  
Multi Phase ◽  
Better Than

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of [Formula: see text]-stage ring-VCO with a resolution of [Formula: see text] in a time period of [Formula: see text]. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40[Formula: see text]nm CMOS process and operates from 1.2[Formula: see text]GHz to 3.6[Formula: see text]GHz with 8-phase outputs. The total lock time is less than 3[Formula: see text][Formula: see text]s including calibration and PLL closed-loop locking processes. Operating at 3.2[Formula: see text]GHz, the in-band phase noise is better than [Formula: see text][Formula: see text]dBc/Hz and root-mean square (RMS) jitter integrated from 10[Formula: see text]KHz to 100[Formula: see text]MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5[Formula: see text]ps and [Formula: see text][Formula: see text]dBc/Hz, respectively. The clock generator consumes only 3[Formula: see text]mW from 1.1[Formula: see text]V supply at high-frequency end and 1.6[Formula: see text]mW at low-frequency end. The active area is only 0.04[Formula: see text]mm2 including on-chip loop filter and auto-calibration circuits.

scholarly journals A 1.8 V 18.13 MHz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1353
Author(s):  
Junsoo Ko ◽  
Minjae Lee
Keyword(s):  
Phase Noise ◽  
Noise Suppression ◽  
Flicker Noise ◽  
Low Frequency ◽  
Cmos Process ◽  
Delay Compensation ◽  
Circuit Delay ◽  
On Chip ◽  
Voltage Feedback ◽  
Transition Voltage

An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency offset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 μ W. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are −60.09 dBc/Hz at 1 kHz with a figure of merit (FOM) of 151.35 dB/Hz, and −106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed oscillator occupies 0.056 mm2 in a standard 0.18 μ m CMOS process.

Optimization of a 61.44 GHz BiCMOS HBT integrated PLL for ultra-fast settling time

2012 ◽  
Vol 4 (4) ◽  
pp. 441-446 ◽  
Author(s):  
Atheer Barghouthi ◽  
Marcu Hellfeld ◽  
Corrado Carta ◽  
Frank Ellinger
Keyword(s):  
Phase Noise ◽  
Settling Time ◽  
Noise Performance ◽  
Carrier Recovery ◽  
Loop Filter ◽  
Loop Bandwidth ◽  
Bicmos Technology ◽  
Phase Noise Performance ◽  
On Chip ◽  
Fast Settling

The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.

Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hole Mobility ◽  
Micro Electro Mechanical System ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Ir Sensor ◽  
Cantilever Structure ◽  
Cmos Mems ◽  
On Chip ◽  
Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis

2021 ◽  
Author(s):  
Baoling Guo ◽  
Seddik Bacha ◽  
Mazen Alamir ◽  
Julien Pouget
Keyword(s):  
Performance Analysis ◽  
Frequency Domain ◽  
Low Frequency ◽  
Experimental Tests ◽  
Frequency Measurement ◽  
Phase Locked Loop ◽  
Frequency Domain Analysis ◽  
Loop Filter ◽  
Control Stability ◽  
Unbalanced Grid

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.

scholarly journals Validation of SCIAMACHY limb NO<sub>2</sub> profiles using solar occultation measurements

2011 ◽  
Vol 4 (4) ◽  
pp. 4753-4800
Author(s):  
R. Bauer ◽  
A. Rozanov ◽  
C. A. McLinden ◽  
L. L. Gordley ◽  
W. Lotz ◽  
...  
Keyword(s):  
The Past ◽  
Middle Latitudes ◽  
Solar Occultation ◽  
Time Period ◽  
Vertical Distributions ◽  
Global Coverage ◽  
Scanning Imaging ◽  
Diurnal Effect ◽  
Better Than ◽  
Balloon Measurements

Abstract. The increasing amounts of reactive nitrogen in the stratosphere necessitates accurate global measurements of stratospheric nitrogen dioxide (NO2). Over the past decade, the SCIAMACHY (SCanning Imaging Absorption spectroMeter for Atmospheric CHartographY) instrument on ENVISAT (European Environmental Satellite) has been providing global coverage of stratospheric NO2 every 6 days, which is otherwise difficult to achieve with other systems (e.g. balloon measurements, solar occultation). In this study, the vertical distributions of NO2 retrieved from limb measurements of the scattered solar light from the SCIAMACHY instrument are validated using NO2 products from three different satellite instruments (SAGE II, HALOE and ACE-FTS). The retrieval approach, as well as the sensitivity of the SCIAMACHY NO2 limb data product are discussed, and the photochemical corrections needed to make this validation feasible, as well as the chosen collocation criteria are described. For each instrument, a time period of two years is analyzed with several hundreds of collocation pairs for each year and instrument. The agreement between SCIAMACHY and each instrument is found to be better than 10 % between 22–24 km and 40 km. Additionally, NO2 amounts in three different latitude regions are validated individually, with considerably better agreements in high and middle latitudes compared to tropics. Differences with SAGE II and ACE-FTS below 20 km are consistent with those expected from the diurnal effect.

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