Digital and Analog Performance of Gate Inside P-Type Junctionless Transistor (GI-JLT)

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation ◽

10.1109/cimsim.2013.70 ◽

2013 ◽

Author(s):

Sangeeta Singh ◽

Pravin Kondekar ◽

Ankit Dixit

Keyword(s):

Analog Performance ◽

Junctionless Transistor ◽

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Charge-plasma based dual-material and gate-stacked architecture of junctionless transistor for enhanced analog performance

Superlattices and Microstructures ◽

10.1016/j.spmi.2015.10.017 ◽

2015 ◽

Vol 88 ◽

pp. 582-590 ◽

Author(s):

S. Intekhab Amin ◽

R.K. Sarin

Keyword(s):

Charge Plasma ◽

Analog Performance ◽

Junctionless Transistor ◽

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A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_15 ◽

2013 ◽

pp. 118-127 ◽

Author(s):

Ratul Kumar Baruah ◽

Roy P. Paily

Keyword(s):

Double Layer ◽

Analog Performance ◽

Junctionless Transistor ◽

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Analog performance of bulk planar junctionless transistor (BPJLT)

10.1109/icccnt.2012.6395875 ◽

2012 ◽

Author(s):

R. K. Baruah ◽

R. P. Paily

Keyword(s):

Analog Performance ◽

Junctionless Transistor

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Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance

International Journal of Materials Mechanics and Manufacturing ◽

10.18178/ijmmm.2019.7.3.448 ◽

2019 ◽

Vol 7 (3) ◽

pp. 144-149

Author(s):

S. C. Wagaj ◽

◽

S. C. Patil

Keyword(s):

Silicon On Insulator ◽

Comparison Study ◽

Analog Performance ◽

Junctionless Transistor ◽

Junction Transistor ◽

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Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Semiconductor Science and Technology ◽

10.1088/1361-6641/abaaed ◽

2020 ◽

Vol 35 (10) ◽

pp. 105022

Author(s):

Vishal Narula ◽

Mohit Agarwal

Keyword(s):

Common Source ◽

Double Gate ◽

Analog Performance ◽

Junctionless Transistor

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The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

Journal of Semiconductors ◽

10.1088/1674-4926/36/9/094001 ◽

2015 ◽

Vol 36 (9) ◽

pp. 094001 ◽

Author(s):

S. Intekhab Amin ◽

R. K. Sarin

Keyword(s):

Double Gate ◽

Analog Performance ◽

Junctionless Transistor ◽

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A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

IEEE Transactions on Electron Devices ◽

10.1109/ted.2013.2292852 ◽

2014 ◽

Vol 61 (1) ◽

pp. 123-128 ◽

Author(s):

Ratul K. Baruah ◽

Roy P. Paily

Keyword(s):

High K ◽

Analog Performance ◽

Junctionless Transistor ◽

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Analog performance investigation of double gate junctionless transistor using spacer layer engineering

2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT) ◽

10.1109/icccnt.2017.8204086 ◽

2017 ◽

Author(s):

Nalineesh Chahal ◽

Gaurav Saini

Keyword(s):

Double Gate ◽

Analog Performance ◽

Spacer Layer ◽

Junctionless Transistor

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Investigation of NBTI Effect in P-Type Junctionless Transistor with Uniform and Graded Doping Profiles

Transactions on Electrical and Electronic Materials ◽

10.1007/s42341-021-00287-3 ◽

2021 ◽

Author(s):

Naheeda Reshi ◽

M. W. Akram ◽

Mudasir Ahmad Sheikh

Keyword(s):

Junctionless Transistor ◽

P Type ◽

Doping Profiles

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Using Source Side Channel Engineering on Junctionless Transistor for Improved Analog Performance

2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE) ◽

10.1109/icrieece44171.2018.9008941 ◽

2018 ◽

Author(s):

Avinash Kranti ◽

Rahul Shandilya ◽

Gaurav Saini

Keyword(s):

Side Channel ◽

Analog Performance ◽

Junctionless Transistor ◽

Channel Engineering

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