A Design Approach of Low Power VLSI for Downsampler Using Multirate Technique

2013 ◽  
Author(s):  
R. M. Rewatkar ◽  
S. L. Badjate
Keyword(s):  
Low Power ◽  
Design Approach

scholarly journals CMOS Buffer Design Approach for Low Power and Lower Delay SRAM Design

2016 ◽  
Vol 25 ◽  
pp. 481-488 ◽  
Author(s):  
p.p. Mariyamol ◽  
N. Aswathy
Keyword(s):  
Low Power ◽  
Design Approach ◽  
Sram Design ◽  
Buffer Design

scholarly journals Power-Saving Design of Radio Frequency Identification Sensor Networks in Bus Seatbelt Monitoring Systems

Sensors ◽  
2020 ◽  
Vol 20 (20) ◽  
pp. 5882
Author(s):  
Sitong Sun ◽  
Wen Yang ◽  
Wilson Wang
Keyword(s):  
Sensor Networks ◽  
Low Power ◽  
Radio Frequency ◽  
Radio Frequency Identification ◽  
Power Saving ◽  
Low Power Design ◽  
Sensor Nodes ◽  
Design Approach ◽  
Registration Method ◽  
Frequency Identification

Seatbelt state monitoring is important in intercity buses for passenger safety. This paper discusses the issues and challenges in power-saving design of radio frequency identification (RFID) sensor networks in bus seatbelt monitoring. A new design approach is proposed in this work for low-power layout and parameter setting in RFID sensor nodes in hardware and software design. A one-to-many pairing registration method is suggested between the concentrator and the seat nodes. Unlike using extra computer software to write seat identification (ID) into an integrated circuit (IC) card, the node ID in this project can be stored into the concentrator directly, which can reduce intermediate operations and reduce development costs. The effectiveness of the proposed low-power design approach is verified by some experimental tests.

scholarly journals Ultra low power design approach of asynchronous delta sigma modulator

2017 ◽  
Vol 7 (1.1) ◽  
pp. 84
Author(s):  
Anil Kumar Sahu ◽  
Rashid Sheikh ◽  
A. Surendar
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Approach ◽  
Ultra Low Power ◽  
Vital Part ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Inverse Operation

Asynchronous Delta Sigma Modulator (ADSM) is assuming an extremely vital part in the majority of conveying device  and information convertor and in this manner requires the exceptional consideration in outlining. The execution of the vast majority of the device having DSM as an essential segment is described by the execution of the DSM hardware. This paper introduces the audit of work performed in planning of Asynchronous Delta Sigma Modulator. Latest trends are about the utilization of ADSM for various applications. Contrasting the execution of various ADSM circuits, an execution paradigm is settled for ADSM plan. The execution criteria basically think about the Low working voltages, low power utilization, high SNDR and better focus recurrence. At that point a strategy is suggested that characterizes the High execution ADSM that influence joined utilization of various methods to like inverse operation and mass driven MOS for ultra low power outline and enhancing the execution of an Asynchronous Delta Sigma Modulator.

A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach

2012 ◽  
Vol 2 (2) ◽  
pp. 322-332
Author(s):  
Hongbo Zhang ◽  
Martin D. F. Wong ◽  
Kai-Yuan Chao ◽  
Liang Deng
Keyword(s):  
Low Power ◽  
Design Approach ◽  
Interconnect Design

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor

IEEE Micro ◽  
2005 ◽  
Vol 25 (5) ◽  
pp. 30-38 ◽  
Author(s):  
T. Asano ◽  
J. Silberman ◽  
S.H. Dhong ◽  
O. Takahashi ◽  
M. White ◽  
...  
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Design Approach ◽  
Cell Processor ◽  
Processor Element ◽  
A Cell ◽  
Embedded Sram
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