The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor

Author(s):  
Jaroslav Sykora ◽  
Lukas Kohout ◽  
Roman Bartosinski ◽  
Leos Kafka ◽  
Martin Danek ◽  
...  
Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 50 ◽  
Author(s):  
Yu-Sian Liu ◽  
Kuei-Ann Wen

This paper presents the design, simulation and mechanical characterization of a newly proposed complementary metal-oxide semiconductor (CMOS)/micro-electromechanical system (MEMS) accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. An approximate analytical model for the spring design is presented. The experiments showed that the resonant frequency of the proposed tri-axis accelerometer was around 5.35 kHz for out-plane vibration. The tri-axis accelerometer had an area of 1096 μm × 1256 μm.


Author(s):  
Roman Bartosiński ◽  
Martin Daněk ◽  
Leoš Kafka ◽  
Lukáš Kohout ◽  
Jaroslav Sýkora
Keyword(s):  

2011 ◽  
Vol 20 (01) ◽  
pp. 71-87 ◽  
Author(s):  
DAVID FITRIO ◽  
SUHARDI TJOA ◽  
ANAND MOHAN ◽  
RONNY VELJANOVSKI ◽  
ANDREW BERRY ◽  
...  

A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.


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