The Architecture and the Technology Characterization of an FPGA-Based Customizable Application-Specific Vector Coprocessor (ASVP)

2013 ◽  
pp. 45-77
Author(s):  
Roman Bartosiński ◽  
Martin Daněk ◽  
Leoš Kafka ◽  
Lukáš Kohout ◽  
Jaroslav Sýkora
Keyword(s):  
Application Specific

scholarly journals Implementation of a CMOS/MEMS Accelerometer with ASIC Processes

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 50 ◽  
Author(s):  
Yu-Sian Liu ◽  
Kuei-Ann Wen
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mems Accelerometer ◽  
Cmos Mems ◽  
Application Specific Integrated Circuit ◽  
Micro Electromechanical System ◽  
Application Specific ◽  
Mems Process

This paper presents the design, simulation and mechanical characterization of a newly proposed complementary metal-oxide semiconductor (CMOS)/micro-electromechanical system (MEMS) accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. An approximate analytical model for the spring design is presented. The experiments showed that the resonant frequency of the proposed tri-axis accelerometer was around 5.35 kHz for out-plane vibration. The tri-axis accelerometer had an area of 1096 μm × 1256 μm.

A CMOS ANALOG INTEGRATED CIRCUIT FOR PIXEL X-RAY DETECTOR

2011 ◽  
Vol 20 (01) ◽  
pp. 71-87 ◽  
Author(s):  
DAVID FITRIO ◽  
SUHARDI TJOA ◽  
ANAND MOHAN ◽  
RONNY VELJANOVSKI ◽  
ANDREW BERRY ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Future Research ◽  
Pulse Shaper ◽  
X Ray ◽  
Application Specific Integrated Circuit ◽  
A Charge ◽  
Czt Detectors ◽  
Cmos Analog Integrated Circuit ◽  
Application Specific

A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.

Evaluation and Characterization of Reliable Packaging Method for Neuromotor Prosthetic Device

2013 ◽  
Vol 651 ◽  
pp. 367-371
Author(s):  
Kwan Ling Tan ◽  
Rui Qi Lim ◽  
Tack Boon Yee ◽  
Ming Yua Cheng
Keyword(s):  
Integrated Circuit ◽  
Three Dimensional ◽  
Electroless Nickel ◽  
Bonding Parameters ◽  
Application Specific Integrated Circuit ◽  
Electrical Connections ◽  
Application Specific ◽  
Test Result ◽  
Probe Array

Neural probe array is used for neural recording and simulation applications. It will be implanted into the motor cortex of a paralytic human to control robotic arm and perform tasks such as grasping an object. The major components are silicon (Si) probes, Si platform, application-specific integrated circuit (ASIC), polyimide flexible cable and wireless IC. In-plane Si probes are inserted into the Si platform to form a three-dimensional (3D) probe array. Wirebonding technique is used to integrate the ASIC and the probe array. Pad finishes play an important role in wire bonding as it would affect the reliability of the electrical connections. As such, the focus of the paper will be on the evaluation and characterization of an electroless nickel immersion gold (ENIG) pad finishing and its bonding parameters for wirebonding application. ENIG pad having a 0.1-µm gold (Au) thickness combined with an additional Au stud and wirebonding temperature of 200 °C are found to have comparable wirebonding capabilities as a 0.3-µm thick Au finishing pad. The wire pull test result and SEM observation between the ENIG and Au finishing pad at different bonding parameters were presented and discussed.

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