scholarly journals Optimized switch-level soft error detection based on advanced switch-level models

2021 ◽  
Author(s):  
Jalal Mohammad Chikhe
Keyword(s):  
Error Detection ◽  
Early Stage ◽  
Soft Errors ◽  
Logic Gate ◽  
Soft Error ◽  
Combinational Circuits ◽  
Single Event Transient ◽  
New Techniques ◽  
Speed Up ◽  
Logic Threshold

Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

scholarly journals Optimized switch-level soft error detection based on advanced switch-level models

2021 ◽  
Author(s):  
Jalal Mohammad Chikhe
Keyword(s):  
Error Detection ◽  
Early Stage ◽  
Soft Errors ◽  
Logic Gate ◽  
Soft Error ◽  
Combinational Circuits ◽  
Single Event Transient ◽  
New Techniques ◽  
Speed Up ◽  
Logic Threshold

Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

scholarly journals An Investigation into Soft Error Detection Efficiency at Operating System Level

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Seyyed Amir Asghari ◽  
Okyay Kaynak ◽  
Hassan Taheri
Keyword(s):  
Operating System ◽  
Error Detection ◽  
Detection Efficiency ◽  
Soft Errors ◽  
Control Flow ◽  
Soft Error ◽  
System Level ◽  
Occurrence Rate ◽  
Transient Errors ◽  
System Components

Electronic equipment operating in harsh environments such as space is subjected to a range of threats. The most important of these is radiation that gives rise to permanent and transient errors on microelectronic components. The occurrence rate of transient errors is significantly more than permanent errors. The transient errors, or soft errors, emerge in two formats: control flow errors (CFEs) and data errors. Valuable research results have already appeared in literature at hardware and software levels for their alleviation. However, there is the basic assumption behind these works that the operating system is reliable and the focus is on other system levels. In this paper, we investigate the effects of soft errors on the operating system components and compare their vulnerability with that of application level components. Results show that soft errors in operating system components affect both operating system and application level components. Therefore, by providing endurance to operating system level components against soft errors, both operating system and application level components gain tolerance.

Full Error Detection and Correction Method Applied on Pipelined Structure Using Two Approaches

2020 ◽  
Vol 29 (13) ◽  
pp. 2050218 ◽  
Author(s):  
Mehmed Dug ◽  
Stefan Weidling ◽  
Egor Sogomonyan ◽  
Dejan Jokic ◽  
Milos Krstic
Keyword(s):  
Error Detection ◽  
Soft Errors ◽  
Correction Method ◽  
Soft Error ◽  
Combinational Logic ◽  
Combinational Circuit ◽  
Multiple Faults ◽  
Error Detection And Correction ◽  
Detection Circuit ◽  
The One

In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.

scholarly journals Robust Face Recognition Against Soft-errors Using a Cross-layer Approach

2016 ◽  
Vol 11 (5) ◽  
pp. 657
Author(s):  
Gu-Min Jeong ◽  
Chang-Woo Park ◽  
Sang-Il Choi ◽  
Kyoungwoo Lee ◽  
Nikil Dutt
Keyword(s):  
Face Recognition ◽  
Embedded System ◽  
Error Detection ◽  
Soft Errors ◽  
Memory Systems ◽  
Recognition System ◽  
Soft Error ◽  
Multimedia Systems ◽  
Cross Layer ◽  
Robust Face Recognition

Recently, soft-errors, temporary bit toggles in memory systems, have become increasingly important. Although soft-errors are not critical to the stability of recognition systems or multimedia systems, they can significantly degrade the system performance. Considering these facts, in this paper, we propose a novel method for robust face recognition against soft-errors using a cross layer approach. To attenuate the effect of soft-errors in the face recognition system, they are detected in the embedded system layer by using a parity bit checker and compensated in the application layer by using a mean face. We present the soft-error detection module for face recognition and the compensation module based on the mean face of the facial images. Simulation results show that the proposed system effectively compensates for the performance degradation due to soft errors and improves the performance by 2.11 % in case of the Yale database and by 10.43 % in case of the ORL database on average as compared to that with the soft-errors induced.

scholarly journals Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors

2021 ◽  
Author(s):  
Mohammad R.S. Javaheri
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Soft Errors ◽  
Error Rates ◽  
Soft Error ◽  
Delay Faults ◽  
Fault Propagation ◽  
Delay Fault ◽  
Wide Range ◽  
Strength Based

Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

scholarly journals Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 749
Author(s):  
Fábio Batagin Armelin ◽  
Lírida Alves de Barros Naviner ◽  
Roberto d’Amore
Keyword(s):  
Radiation Effects ◽  
Estimation Error ◽  
Soft Errors ◽  
Soft Error ◽  
The Other ◽  
Single Event ◽  
Single Event Transient ◽  
Logic Simulation ◽  
Advantages And Disadvantages ◽  
Simulation Based

Soft-Error Vulnerability (SEV) is a parameter used to evaluate the robustness of a circuit to the induced Soft Errors (SEs). There are many techniques for SEV estimation, including analytical, electrical and logic simulations, and emulation-based approaches. Each of them has advantages and disadvantages regarding estimation time, resources consumption, accuracy, and restrictions over the analysed circuit. Concerning the ionising radiation effects, some analytical and electrical simulation approaches take into account how the circuit topology and the applied input patterns affect their susceptibilities to Single Event Transient (SET) at the gate level. On the other hand, logic simulation and emulation techniques usually ignore these SET susceptibilities. In this context, we propose a logic simulation-based probability-aware approach for SEV estimation that takes into account the specific SET susceptibility of each circuit gate. For a given operational scenario, we extract the input patterns applied to each gate and calculate its specific SET susceptibility. For the 38 analysed benchmark circuits, we obtained a reduction from 15.27% to 0.68% in the average SEV estimation error, when comparing the estimated value to a reference obtained at the transistor level. The results point out an improvement of the SEV estimation process by considering the specific SET susceptibilities.

scholarly journals Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors

2021 ◽  
Author(s):  
Mohammad R.S. Javaheri
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Soft Errors ◽  
Error Rates ◽  
Soft Error ◽  
Delay Faults ◽  
Fault Propagation ◽  
Delay Fault ◽  
Wide Range ◽  
Strength Based

Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

DESIGN FLOW OF CONCURRENT ERROR DETECTION SCHEMES FOR COMBINATIONAL CIRCUITS

2018 ◽  
Vol 65 ◽  
pp. 92-98
Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  
Keyword(s):  
Error Detection ◽  
Design Flow ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Schemes
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