Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications

2016 ◽  
Author(s):  
Charlotte Frenkel ◽  
Jean-Didier Legat ◽  
David Bol
Keyword(s):  
Comparative Analysis ◽  
Error Detection ◽  
Low Cost ◽  
Soft Error ◽  
Space Applications

scholarly journals Comparative analysis of soft-error detection strategies

2018 ◽  
Author(s):  
Gokcen Kestor ◽  
Burcu Ozcelik Mutlu ◽  
Joseph Manzano ◽  
Omer Subasi ◽  
Osman Unsal ◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Error Detection ◽  
Soft Error ◽  
Detection Strategies

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

Robust Test Method of TSOP PEMs for Space Application

2019 ◽  
Author(s):  
Yasunobu Iwai ◽  
Koichi Shinozaki ◽  
Daiki Tanaka
Keyword(s):  
Evaluation Method ◽  
Low Cost ◽  
Reliability Evaluation ◽  
Test Method ◽  
Thermal Shock Test ◽  
Space Application ◽  
Space Applications ◽  
Limit Test ◽  
Long Time ◽  
Short Time

Abstract Compared with space parts, consumer parts are highly functional, low cost, compact and lightweight. Therefore, their increased usage in space applications is expected. Prior testing and evaluation on space applicability are necessary because consumer parts do not have quality guarantees for space application [1]. However, in the conventional reliability evaluation method, the test takes a long time, and the problem is that the robustness of the target sample can’t be evaluated in a short time. In this report, we apply to the latest TSOP PEM (Thin Small Outline Package Plastic Encapsulated Microcircuit) an evaluation method that combines preconditioning and HALT (Highly Accelerated Limit Test), which is a test method that causes failures in a short time under very severe environmental conditions. We show that this method can evaluate the robustness of TSOP PEMs including solder connections in a short time. In addition, the validity of this evaluation method for TSOP PEM is shown by comparing with the evaluation results of thermal shock test and life test, which are conventional reliability evaluation methods.

Setting an error detection infrastructure with low cost acoustic wave detectors

2012 ◽  
Vol 40 (3) ◽  
pp. 333-343 ◽  
Author(s):  
Gaurang Upasani ◽  
Xavier Vera ◽  
Antonio González
Keyword(s):  
Acoustic Wave ◽  
Error Detection ◽  
Low Cost

scholarly journals Comparative Analysis of Low-Cost GNSS OEM Board K706 AND BX316 (Case Study: Bulusidokare Village Sidoarjo Regency)

2021 ◽  
Vol 731 (1) ◽  
pp. 012024
Author(s):  
M N Cahyadi ◽  
E Y Handoko ◽  
R Mardiyanto ◽  
I M Anjasmara ◽  
Khomsin ◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Low Cost

scholarly journals Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection

2014 ◽  
Vol 11 (3) ◽  
pp. 1-24
Author(s):  
Gulay Yalcin ◽  
Oguz Ergin ◽  
Emrah Islek ◽  
Osman Sabri Unsal ◽  
Adrian Cristal
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Fine Grained

scholarly journals Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs

Electronics ◽  
2018 ◽  
Vol 7 (9) ◽  
pp. 163 ◽  
Author(s):  
Honorio Martin ◽  
Pedro Martin-Holgado ◽  
Yolanda Morilla ◽  
Luis Entrena ◽  
Enrique San-Millan
Keyword(s):  
Low Cost ◽  
Ring Oscillator ◽  
Radiation Environment ◽  
Key Generation ◽  
Total Ionizing Dose ◽  
Space Applications ◽  
Physical Unclonable Functions ◽  
Dose Effects ◽  
Total Ionizing Dose Effects

Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly being used for authentication and key generation in ICs and FPGAs. For space systems, they are a promising approach to meet the needs for secure communications at low cost. To this purpose, it is essential to determine if they are reliable in the space radiation environment. In this work we evaluate the Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring Oscillator PUF. Several major quality metrics have been used to analyze the evolution of the PUF response with the total ionizing dose. Experimental results demonstrate that total ionizing dose has a perceptible effect on the quality of the PUF response, but it could still be used for space applications by making some appropriate corrections.

scholarly journals Optimized switch-level soft error detection based on advanced switch-level models

2021 ◽  
Author(s):  
Jalal Mohammad Chikhe
Keyword(s):  
Error Detection ◽  
Early Stage ◽  
Soft Errors ◽  
Logic Gate ◽  
Soft Error ◽  
Combinational Circuits ◽  
Single Event Transient ◽  
New Techniques ◽  
Speed Up ◽  
Logic Threshold

Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

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